Using a single channel on an ad9361 to receive, there are 12-bits of I and 12-bits of Q. In 2016_R2 we packed some extra data into the upper four bits of I and Q. In 2018_R2 we are using a simliar method but are suspecting it is being overwritten with a sign extension of the 12th bit. Our logic occurs before the CPack module. Is there anything new that would be causing this problem?
In what point of the data path do you add these 4 bits to the samples?
We are stuffing the bits just before the wfifo. So the blocks that could be affecting it are the wfifo, the cpack, or the ADC DMA
It turns out this was an issue in the software, not the firmware