My platform is ZCU102 + ADRV9375 and I have sucessfully run the HDL_2018_R2 No-OS project on the GitHub. Now, I want to build my own project based on this.
The current transmitting path should be : ZYNQ (PS) -> DMA -> ADI IP Cores -> JESD -> ADRV9375. I hope that my transmitting data can be generated from a customized PL (FPGA) module, which means the transmitting path should be modified to : PL -> ADI IP Cores -> JESD -> ADRV9375.
Now, I don't kow which node of transmitting path should be cut in, and how should the corresponding clock signal and data format be set ? In addition, after doing this, what effect will it have on the initialization of ADRV9375, and do I need to modify the Mykonos codes ?
I hope you can give me some help or advice.
According to your advice, I have connected my data generator to the axi stream interface of TPL core, but the transmitting port still has no output signal. I suspect that the drive clock frequency may not be set correctly. I opened the block design in the project and found that the clocks that drive the DAC-related modules are generated by the axi_ad9371_clkgen module. If the configuration in mykonos is as shown below, what is the clock frequency generated by the axi_ad9371_clkgen module ?
In addition, should the generated data be triggered by the rising edge or falling edge of the clock ?
Another problem is, according to the data sheet of AD9375, its maximum transmitting power should be about 5dBm, but at present my maximum transmitting power is only -5dBm. Iwant to konw how to adjust the gain of the transmitting path, which seems to be unconfigurable in the TES software.
Hi Stanley,Sorry for the late reply.The axi_ad9371_clkgen clock frequency should be the device clock frequency (122.88) because you have 2 channels and 2 lanes on the JESD interface. But I would not go that far for now.First, can you post your UART messages? From those you should get:- is the JESD link up- status/clock frequencyWhat data path do you have selected for the Tx (REG_CHAN_CNTRL_7 on all channels)?Rising edge.Regarding the transmit power, how have you measured it?
This is my UART messages:
And this is my settings in headless.c file:
I have replaced the clk_0 signal generated by the axi_ad9371_tx_clkgen module with the external input clock signal DAC_CLK at a frequency of 122.88 MHz. The connection of the DAC_CLK signal to other modules is consistent with the clk_0 signal.
At the same time, as shown below, I have replaced the four dac_data signals generated by the axi_ad9371_tx_upack module with the external four input DAC_DATA signals and connected them directly to the axi_ad9371_core module.
My TES software configuration is as follow:
In addition, the dac_fifo_bypass signal in the HDL project is set to 0. But the Tx output port still has no signal.
The strange thing is that when my DAC_CLK signal is set to 61.44 MHz, which is consistent with the frequency of the DAC_DATA signals, the deframer status does not appear in the UART message. At the same time, the Tx port can have the correct output signal, bu the spectrum will be constantly changing and interrupting.
Regarding the transmit power, I measured by connecting the Tx port directly to the spectrum analyzer.
I have not changed for any settings of JESD Lane. But accroding to the default settings of the TES and HDL project, Tx should have 4 lands.
In Tx, I used both Tx1 and Tx2, including (i0, q0, i1, q1). According to my TES settings, my IQRate = 122.88 MSPS. So I used 122.88 MHz as my clock source to drive the Cordic module to generate a cosine signal with a frequency of 10 MHz. The bit width of this signal is 16 bits.
Because the input of axi_ad9371_core module is two consecutive samples of 16 bits. So I packaged two consecutive 16-bit samples generated by Cordic module into a 32-bit signal.The update rate of the packaged signal is 61.44 MHz = 122.88 MHz / 2.
Oddly enough, at this time, if the clock signal input to axi_ad9371_core is not 122.88 MHz, but 61.44 MHz, the Tx port can output a cosine singal 10 MHz away from the center frequency. But this signal is not stable. Observing from the spectrum analyzer, the signal power is constantly changing.
I don't konw where the problem is, I need your kind help and advice.