About Tx Path of AD9375 No-os Setup

Hello,

    My platform is ZCU102 + ADRV9375 and I have sucessfully run the HDL_2018_R2 No-OS project on the GitHub. Now, I want to build my own project based on this.

    The current transmitting path should be : ZYNQ (PS) -> DMA -> ADI IP Cores -> JESD -> ADRV9375. I hope that my transmitting data can be generated from a customized PL (FPGA) module, which means the transmitting path should be modified to : PL -> ADI IP Cores -> JESD -> ADRV9375.

   

    Now, I don't kow which node of transmitting path should be cut in, and how should the corresponding clock signal and data format be set ?  In addition, after doing this, what effect will it have on the initialization of ADRV9375, and do I need to modify the Mykonos codes ?

    I hope you can give me some help or advice.

Thanks,

Stanley

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  • 0
    •  Analog Employees 
    on Aug 14, 2019 8:15 AM over 1 year ago

    Hi Stanley,

    I think the easiest way is to connect your data generator to the AXI stream interface of the TPL core (https://github.com/analogdevicesinc/hdl/blob/hdl_2018_r2/library/axi_ad9371/axi_ad9371.v#L96-L107).

    -Istvan

  • Hello Csoml,

        Thanks for your reply and your work for building the GitHub project. I really appreciate it.

        I have browsed the corresponding source code, but here I have three questions:

            1. Because the quantization bits of AD9375 should be 14, and the data width of each dac_data port is 32, does it mean that the remaining 18 bits can be ignored ?

            2. Should the frequency of dac_clk signal be the same as that set in Mykonos ?

            3. Should the calibration process in Mykonos be disabled, because suan an operation may invalidate it ?

    Regards,

    Stanley

  • Hello, Andrei

        Thanks for your reply.

        The current situation is:

            Case1: I used the Xilinx Clock wizard outside the HDL Block Design to generate a 61.44MHz clock signal, and then input this clock signal into Block Design to replace the clock signal generated by axi_ad9371_tx_clkgen. At this time, the Tx output signal generated by the DDS is not stable. Deframer Status also appears in the UART Message.

            Case2: No modifications are made to HDL Block Design. At this time, the Tx output signal generated by the DDS is stable.

        My question is, what is the difference between the 61.44MHz clock signal generated by the Xilinx Clock Wizard and the clock signal generated by axi_ad9371_tx_clkgen?

    Regards,

    Stanley

  • 0
    •  Analog Employees 
    on Sep 27, 2019 3:38 PM over 1 year ago in reply to StanleyHuang

    Hi,

    You might not have a fixed relationship between the device clock(the clock coming from the xcvr).
    You are moving data across 2 clock domains without proper logic.

    What do you use as a source for the clock wizard?
    It is not clear to me do you still use the axi_ad9371x_clkgen with the clock wizard... Do you have timing problems?

    Regards,
    Andrei

  • Hi, Andrei

        Thanks for your reply.

       

         As shown in the figure, I used the ZCU102 onboard signal (user si570 sysclk) as reference clock of the Clock Wizard in the Top Module to generate a clock signal of 122.88MHz. I use this clock to drive the Signal Generator and send the output signal to the FIFO.

        This FIFO is an Asymmetric Port Width FIFO that performs a serial-to-parallel conversion function that converts the 16-bit 122.88 MSPS signal I input into a 32-bit 122.88 MSPS signal. Then use the clock signal generated by ad9371_tx_clkgen to read the FIFO. With this FIFO module, it should be possible to synchronize the signals of two different clock domains. However, as can be seen from the Tx output spectrum, the output signal still has the previously mentioned instability.

        I would like to ask if there is any good way to solve this problem. Because the 61.44MHz clock signal is actually difficult to generate a signal of 122.88MSPS. In addition, is there any way to generate a 122.88MHz clock signal that can be synchronized with the modules in XCRV and Block Design or in the same clock domain.

    Regards,

    Stanley

  •     Or can you tell me how to adjust the number of JESD Lanes from 4 Lanes to 2 Lanes and the corresponding data format ? Thus, with one sample per clock cycle, I can use the clk generated by the tx_clkgen to drive my signal generator

    Regards,

    Stanley

  • +1
    •  Analog Employees 
    on Oct 23, 2019 12:42 PM over 1 year ago in reply to StanleyHuang

    Hi,

    Sorry for the late reply.
    Your problem might be caused by different clock sources.
    Solutions for generating the 122.88MHz clock:
    - use the second clock output of the ad9371_tx_clkgen to out the 122.88 clk.
    - use as reference the 61.44MHz clock of ad9371_tx_clkgen to your clock wizard.

    You can use 2 lanes, for this take a look at:
    https://wiki.analog.com/resources/fpga/docs/hdl/generic_jesd_bds

    Andrei

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