My platform is ZCU102 + ADRV9375 and I have sucessfully run the HDL_2018_R2 No-OS project on the GitHub. Now, I want to build my own project based on this.
The current transmitting path should be : ZYNQ (PS) -> DMA -> ADI IP Cores -> JESD -> ADRV9375. I hope that my transmitting data can be generated from a customized PL (FPGA) module, which means the transmitting path should be modified to : PL -> ADI IP Cores -> JESD -> ADRV9375.
Now, I don't kow which node of transmitting path should be cut in, and how should the corresponding clock signal and data format be set ? In addition, after doing this, what effect will it have on the initialization of ADRV9375, and do I need to modify the Mykonos codes ?
I hope you can give me some help or advice.
I think the easiest way is to connect your data generator to the AXI stream interface of the TPL core (https://github.com/analogdevicesinc/hdl/blob/hdl_2018_r2/library/axi_ad9371/axi_ad9371.v#L96-L107).
Thanks for your reply and your work for building the GitHub project. I really appreciate it.
I have browsed the corresponding source code, but here I have three questions:
1. Because the quantization bits of AD9375 should be 14, and the data width of each dac_data port is 32, does it mean that the remaining 18 bits can be ignored ?
2. Should the frequency of dac_clk signal be the same as that set in Mykonos ?
3. Should the calibration process in Mykonos be disabled, because suan an operation may invalidate it ?
1. In 32 bits you will have two consecutive samples, each stored in 16 bits. Just shift your 14 bit value to left with two bits or just simply generate 16 bits values and be awear that the two least significat bits will be ignored.
2. You have to drive your module using the dac_clk clock signal. Which will be the same than the one set in Mykonos.
3. You should not disable the calibration process.
Suppose that the two consecutive samples that need to be sent are sample1 and sample2, and their data depth is 14 bits. For simplicity, filling 0 at the end of sample1 and sample2 to extend them to 16 bits. Finally, they are combined into a 32-bit dac_data signal. The timing of the dac_data signal and the dac_clock signal is as shown in the figure below. Is this correct ?
It should be MSB aligned. Meaning, when you extend the samples, you add 2 bits to the least significant side. Also, the least significant 16 bits will store the first sample, and a most significant 16 bits the second one.
According to your advice, I have connected my data generator to the axi stream interface of TPL core, but the transmitting port still has no output signal. I suspect that the drive clock frequency may not be set correctly. I opened the block design in the project and found that the clocks that drive the DAC-related modules are generated by the axi_ad9371_clkgen module. If the configuration in mykonos is as shown below, what is the clock frequency generated by the axi_ad9371_clkgen module ?
In addition, should the generated data be triggered by the rising edge or falling edge of the clock ?
Another problem is, according to the data sheet of AD9375, its maximum transmitting power should be about 5dBm, but at present my maximum transmitting power is only -5dBm. Iwant to konw how to adjust the gain of the transmitting path, which seems to be unconfigurable in the TES software.
Hi Stanley,Sorry for the late reply.The axi_ad9371_clkgen clock frequency should be the device clock frequency (122.88) because you have 2 channels and 2 lanes on the JESD interface. But I would not go that far for now.First, can you post your UART messages? From those you should get:- is the JESD link up- status/clock frequencyWhat data path do you have selected for the Tx (REG_CHAN_CNTRL_7 on all channels)?Rising edge.Regarding the transmit power, how have you measured it?