About Tx Path of AD9375 No-os Setup


    My platform is ZCU102 + ADRV9375 and I have sucessfully run the HDL_2018_R2 No-OS project on the GitHub. Now, I want to build my own project based on this.

    The current transmitting path should be : ZYNQ (PS) -> DMA -> ADI IP Cores -> JESD -> ADRV9375. I hope that my transmitting data can be generated from a customized PL (FPGA) module, which means the transmitting path should be modified to : PL -> ADI IP Cores -> JESD -> ADRV9375.


    Now, I don't kow which node of transmitting path should be cut in, and how should the corresponding clock signal and data format be set ?  In addition, after doing this, what effect will it have on the initialization of ADRV9375, and do I need to modify the Mykonos codes ?

    I hope you can give me some help or advice.



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