Unexpected Signals with ML605 FPGA & AD9129

Hello,

 

I'm a new Analog Devices user trying to use the following Reference Design from Analog Devices with their AD9129 Evaluation Board and DAC-FMC Interposer with the Xilinx ML-605 FPGA and ISE Design Suite 14.7 found at this link:

 

https://wiki.analog.com/resources/fpga/xilinx/interposer/ad9129

 

Using the Reference Design above, I am able to output the depicted 300 MHz tone. However, I wanted to take this design and modify it to make this device output any desired waveform in the 1.4 GHz range.

 

Starting with the ML605 Source files found on the Analog Devices webpage above, I open the project in Xilinx Platform Studio and update the cores, then close XPS and run the CORE Generator to regenerate the cores. Next, I configure the Verilog files to include a LUT of 288 values to be converted by the FPGA and digital-analog converter (DAC) to a continuous voltage signal.

 

The problem I am having is when I use this modification to include a lookup table (LUT) and try to send out a signal with the AD9129. While XPS is able to compile the full bitstream, the DAC device outputs unexpected signals. I have several images depicting the pre-generated waveforms I am expecting out of this device and the actual outputs I am seeing on an oscilloscope.

 

I have tried changing the LUT values within the same project to see if the signals change and correct themselves, but they do not. Creating brand new projects by restarting the whole process also yields the exact same unexpected signals.

 

I am considering changing my workstation and starting with a clean installation of the ISE Design Suite to see if there may be a problem with XPS updating the wrong files/libraries/projects. But I wanted to post here to ask if anyone can point out anything I may have missed or help out in any way.

 

I appreciate all and any help, thank you.

Parents Reply
  • By new configuration, I meant that you configuring the device (AD9219) differently, to mix your base band signal to 1.4 GHz. 

    The provided reference design is using the DDS as data source:

    Xil_Out32((CF_BASEADDR + 0x04), 0x00000);
    Xil_Out32((CF_BASEADDR + 0x04), (0x10001 | ad9129_dds_count(300, 2800)));

    xil_printf("done.\n\r");

Children
  • // ***************************************************************************
    // ***************************************************************************
    // ***************************************************************************
    // ***************************************************************************
    
    #include <stdio.h>
    #include "platform.h"
    #include "xbasic_types.h"
    #include "xstatus.h"
    #include "xil_io.h"
    #include "xparameters.h"
    #include "xuartlite_l.h"
    
    #define CF_BASEADDR   XPAR_AXI_AD9129_0_BASEADDR
    #define UART_BASEADDR XPAR_RS232_UART_1_BASEADDR
    
    // ***************************************************************************
    // ***************************************************************************
    
    extern char inbyte(void);
    void xil_printf(const char *ctrl1, ...);
    
    void delay_ms(u32 ms_count) {
      u32 count;
      for (count = 0; count < ((ms_count * 100000) + 1); count++) {
        asm("nop");
      }
    }
    
    u32 user_exit(void) {
      while (!XUartLite_IsReceiveEmpty(UART_BASEADDR)) {
        if (XUartLite_RecvByte(UART_BASEADDR) == 'q') {
          return(1);
        }
      }
      return(0);
    }
    
    // clocks must be in mhz
    
    u32 ad9129_dds_count(u32 sin_clk, u32 dac_clk) {
      if (sin_clk > (dac_clk/2)) {
        xil_printf("sin(%d) over NS rate(%d)\n\r", sin_clk, dac_clk);
      }
      return((65536 * sin_clk)/dac_clk);
    }
    
    // ***************************************************************************
    // ***************************************************************************
    
    void updateWaveform(unsigned int addr, unsigned int val) {
      Xil_Out32((CF_BASEADDR+0x08), addr);
      Xil_Out32((CF_BASEADDR+0x0C), val);
    }
    
    int main() {
      unsigned int dds_freq;
      int i;
    
      init_platform();
      print("Starting up.\n\r");
      delay_ms(20);
      for (i=0;i<288;i++) {
    	  updateWaveform(i, 8192);
      }
      updateWaveform(100, 16383);
      updateWaveform(101, 1);
      dds_freq = 300;
      // after mu locked, program the dds (so that it's serdes is out of reset).
      while(1) {
    /*	  	  while(1) {
    		  xil_printf("DDS step frequency : %d MHz\n\r", dds_freq);
    		  Xil_Out32((CF_BASEADDR + 0x04), 0x00000);
    		  Xil_Out32((CF_BASEADDR + 0x04), (0x10001 | ad9129_dds_count(dds_freq, 2800)));
    		  delay_ms(20);
    		  dds_freq = dds_freq + 100;
    		  delay_ms(20);
    		  if (dds_freq > 1000) break;
    	  }*/
    	  xil_printf("Switching to the original impulse.\n\r");
    	  Xil_Out32((CF_BASEADDR + 0x04), (0x1<<16) | (0x1<<31));
    	  //xil_printf("Switching to the second impulse.\n\r");
    	  //Xil_Out32((CF_BASEADDR + 0x04), (0x1<<31) | (0x1<<16));
    
    	  delay_ms(200);
    	  dds_freq = 200;
    	  xil_printf("Switching back to sine wave.\n\r");
    	  //Xil_Out32((CF_BASEADDR + 0x04), 0x00000);
    	  //Xil_Out32((CF_BASEADDR + 0x04), (0x10001 | ad9129_dds_count(dds_freq, 2800)));
    	  delay_ms(200);
    
      }
    
      cleanup_platform();
    
      return(0);
    }
    
    // ***************************************************************************
    // ***************************************************************************
    

    Here's the C design code that we are using for the first pair of images. We've added lines along with using the DDS to include data coming from our LUT. It's a little rough to read so I apologize in advance.