JESD204 questions

Good morning

I am trying to understand the problem definitions for JEsSD204. I read lot of documentation and I am able to follow most of the content, but the definition of the
terms is not clear to me.
First what is meant with Latency and deterministic Latency.

The chain that produces delays adds: The ADC Core Latency, The RX Delay (Serialized, The Lane Delay), The deSerializer.

What is not deterministic appears to me only the Lane delay, all of the rest is known and repeatable. But just fix me if that's not the case.

Whatever is the result of the previous question the final elastic buffer takes care of compensating the different arrival time of serial data, in my understanding the incoming bits are stored as thety arrive in each lane, and are serialized out of the elastic buffer all together when they are supposed to be there entirely.
Reading the page 15 of the document JESD204B Survival Guide, I see the Subclass 0 has the synchronization steps, so effectively this provides a time alignment of different lanes. It is perfectly able to provide a latency compensation. So now I do not follow what is missing in this Subclass 0 respect to the other subclasses.
The device ADC has a frame reference, if all of the ADC share the same signal, they are supposed to be synchronized. Of course I do not understand some of the definitions in the problem. 

Just drop suggestion ..

Thank You

Pietro

Parents
  • Hi Pietro,

    From wikipedia:

    "In mathematics, computer science and physics, a deterministic system is a system in which no randomness is involved in the development of future states of the system.[1] A deterministic model will thus always produce the same output from a given starting condition or initial state.[2]"

    In our case this means, after every single bootup of the system you get the same latency on the JESD204B interface. If you're using the interface in Subcalss0 mode, as you mentioned, the receiver using the elastic buffer and the initialization sequence of the protocole, will do the alignment of the data coming from different lanes without a problem. But, because the lane delay (and not just...) is non-deterministic and PVT dependent (process/voltage/temperature) you never going to have the same latency after each power-up cycle.  And the differences can be quite high. (multiple multiframe cycles) There are several applications like RADAR or LIDAR, where it's a fundemantal requirment to know the exact latency of the interface and this latency must be constant.

    This is why in Subclass1 we're using an aditional synchronization signal (SYSREF), which has a fixed relationship with the device clocks and provides a deterministic realease point for the elastic buffer, which can provide a big enough margine to absorbe the non-deterministic delays on the interface.

    Hope this clarifies some doubts,

    -Istvan

Reply
  • Hi Pietro,

    From wikipedia:

    "In mathematics, computer science and physics, a deterministic system is a system in which no randomness is involved in the development of future states of the system.[1] A deterministic model will thus always produce the same output from a given starting condition or initial state.[2]"

    In our case this means, after every single bootup of the system you get the same latency on the JESD204B interface. If you're using the interface in Subcalss0 mode, as you mentioned, the receiver using the elastic buffer and the initialization sequence of the protocole, will do the alignment of the data coming from different lanes without a problem. But, because the lane delay (and not just...) is non-deterministic and PVT dependent (process/voltage/temperature) you never going to have the same latency after each power-up cycle.  And the differences can be quite high. (multiple multiframe cycles) There are several applications like RADAR or LIDAR, where it's a fundemantal requirment to know the exact latency of the interface and this latency must be constant.

    This is why in Subclass1 we're using an aditional synchronization signal (SYSREF), which has a fixed relationship with the device clocks and provides a deterministic realease point for the elastic buffer, which can provide a big enough margine to absorbe the non-deterministic delays on the interface.

    Hope this clarifies some doubts,

    -Istvan

Children