I want to integrate these coefficient ( https://github.com/analogdevicesinc/iio-oscilloscope/blob/master/filters/61_44_28MHz.ftr ) in HDL path of the reference design . i am following this link (https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt) . From this I get to know that FIR(decimator ) should be inserted in RX path and interpolator in Tx path . but my objective is not to decimate or interpolate the data . I just want to insert filter coefficient to uplift band of interest from the noise floor to suppress out of band signal
The only difference would be the clock for the pack cores. It would be the same as the input to your FIR.
is the source code/IPs changes as I didn't found .util_ad9361_adc_fifo and util_ad9361_adc_pack , I believe the design has been upgraded by ADI .if I am right .then kindly update this starting guide . I am using https://github.com/analogdevicesinc/hdl/tree/adrv9361z7035_ccfmc_util_axis_fifo_rx_example.
The example is provided "as is" and not maintained with each update of the hdl repository. It is expected that users use the project as reference and do their own modifications starting from that.
Sorry for giving you further trouble but I want to rephrase my issue and objective.
1- Objective is to generate BW of 20 Mhz or from the chip . I am passing the detected frequency(tone) in particular band and DDS is regenerate it . Now I want that whenever a detected peak is passed to DDS ,so instead of regenerating a single tone . The DDS + Chip generate a BW 20 Mhz , and this all work should be performed in HDL path . As there are example provided by ADI for chip level filter. So I want to learn and implement that how these perform be implemented ????
I'm not totally sure what you are asking here.
However, if you are implementing things purely from vivado (no external tools) then the filter example (which you linked) is the only example that uses that tool flow.