Hi, I'm using adrv9361-z7035 with this (https://github.com/analogdevicesinc/hdl/tree/adrv9361z7035_ccfmc_util_axis_fifo_rx_example) HDL version. Vivado 2017.4.1 had a bug that caused vivado to crash abnormally. Xilinx support recommended me to use 2019.1 which i'm using now. Additionally, I have added my own logic and IPs to reference design. But my design fails timing constraints.(timing report is attached).
WNS=-5.439
TNS=-2.95.954
Also i got some suspicious critical warnings
[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_cells -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}]'. [/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc":9]
[Common 17-55] 'get_property' expects at least one object. ["/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc":13]
Can you help me resolve this problem?