I'm working with the ADRV9009 FPGA reference design. I'm facing a problem with the clock constraints.
The rx_clk_out from the JESD IP is connected to an AXI_CLKGEN IP which is then connected to all my receiver IPs. I'm working with 122.88 Msps on the Rx. So, the clock period should be around 8.138 ns. However, the axi_rx_clkgen output, named mmcm_clk_0_s, is taken to be 5 ns by the design. Due to this, my design fails timing. I would like to specify the correct frequency in the constraints but the problem is that this is a derived clock.
In implemented design, I find that it is derived as qpllch2clk -> divide by 20 -> rx_out_clk_2 -> divide by 1 -> mmcm_clk_0_s. The problem is the period of qpllch2clk is set to 0.25 ns (4 GHz??) Due to this, the mmcm_clk_0_s is set to 5 ns. Where do I change qpllch2clk to the correct value?
If you don't want to support maximum rates on all interfaces you could change constraints from: https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009/zcu102/system_constr.xdc#L83
In the clockgen IP you can manually change the Clkin Period to 8 and VCO Mul to 8 and clk0 Div to 8 so that VCO is in the range 800-1600 and the system works correctly.
What branch of the project are you using ?
The problem is that the clkin period parameter gets ignored. Like I said, Vivado calculates the period as being derived from qpllch2clk and this is set to 0.25 ns.
I cloned the master branch about 8 months ago. Are you saying the current master branch resolves this issue?
I've just built the project with more recent source files and for me the qpllch2clk is 10Gbps when the reference clock is 250, which is more in tune with my expectations.
Given that we force the output clock of util_adxcvr to a certain value and it's basically a copy of the reference clock and not derived from QPLL (based on sysclksel and outclocksel), the timing analysis should be based on that and not have anything to do with QPLL.