Clock constraints in ADRV9009


I'm working with the ADRV9009 FPGA reference design. I'm facing a problem with the clock constraints.

The rx_clk_out from the JESD IP is connected to an AXI_CLKGEN IP which is then connected to all my receiver IPs. I'm working with 122.88 Msps on the Rx. So, the clock period should be around 8.138 ns. However, the axi_rx_clkgen output, named mmcm_clk_0_s, is taken to be 5 ns by the design. Due to this, my design fails timing. I would like to specify the correct frequency in the constraints but the problem is that this is a derived clock.

In implemented design, I find that it is derived as qpllch2clk -> divide by 20 -> rx_out_clk_2 -> divide by 1 -> mmcm_clk_0_s. The problem is the period of qpllch2clk is set to 0.25 ns (4  GHz??) Due to this, the mmcm_clk_0_s is set to 5 ns. Where do I change qpllch2clk to the correct value?