I have been asked to start a new thread as my previous query was resolved.
I am working on AD9364 with Kintex7 XC7K410TFBG900-1. I am using the No-OS Driver in DMA mode. I am able to transmit and receive the sine_lut array in the driver file dac_core.c. I have loopbacked externally the TX and RX channels of AD9364 via SMA cable with attenuator.
My aim is to transmit my FSK Modulated data via AD9364, receive back the same on RX Channel, Demodulate it using my custom written FSK Demodulator IP and recover my original data.
I have verified the FSK Mod->FSK Demod link to confirm that both my FSK IPs are working.
Now I have connected FSK Modulation output to dac_data_i0 channel of AD9361 IP. The output of AD9361 adc_data_i0 channel is connected to FSK Demodulation. When I observe AD9361 i0 output (which is input to FSK Demod) on ILA, I dont observe any sine wave. My FSK input data is at 100KHz. FSK Modulation outputs 1MHz and 1.15MHz. Below is a snapshot of my Vivado Block Design. I have highlighted the important signals. I also tried connecting FSK Modulation output of 16bits with 0 padding to the 64bit input of util_ad9361_dac_upack IP. But still, my result is same.
In my AD9361 driver, I have set the TX LO frequency to 2.4GHz and RX Samp Rate to 10MHz.
Thanks and Regards,
Hi,The AD9361 works with complex modulated signals, a pair of I and Q wiki.analog.com/.../math
We have an example with QPSK
Also, take a look at
The examples you have provided requires MATLAB. I want to modify the existing kc705 reference design using Vivado only.
I have generated my FSK Modulator and FSK Demodulator using DDS Compiler IP from Xilinx. I want to know the data rate of the "util_upack" IP. The input to this upack IP is 64 bit. In what form is the data fed to it? Also, the I0 and Q0 output of AD9361 IP is at what rate?
I want to know this as I want to give the output of AD9361 IP to my FSK Demodulator.
Hi,If you want to transmit data only on I and the Q is 0. You have to deactivate some I/Q imbalance feature from the AD9361.But again, this approach is wrong, the AD9361 is designed for quadrature modulation.Andrei
The FSK Modulator I have generates I-Q data. I connected this I-Q to the AD9361 IP's I0-Q0 channels. Upon checking the output of AD9361 IP and the output of util_ad9361_adc_pack IP, the output doesnt give me downcoverted sine wave at either of the mentioned ports.
After this, I focussed on the AD9361 No-OS Driver. It is seen that the sine_lut data is written in DDR which is being transmitted by the DMA to UPACK to AD9361. I want to replace this sine_lut with my FSK I-Q data. So how do I write it to DDR?
If you dont recommend this, how do I connect my I-Q data directly to AD9361 so that upon receiving back the data via external loopback, I can recover my input FSK data?
Hi,You say you have the I and Q connected to the axi_ad9361, so you changed the modulator IP(the block design above is outdated, right)?There are a few EZ threads that can help, on how to transmit custom data in no-OS.https://ez.analog.com/fpga/f/q-a/32372/ad9361---send-my-own-data-i-q