I am using HDL_2016_R2 on cyclone V SOC platform
during compilation of the design i am facing timing violation error. I am attaching the error message.
Please help me to resolve the issue.
Can you try using the latest release ? This is an old release for which we cannot provide support.
I have quartus2 ver16.1 only.
Does your latest version is compatible with quartus2 16.1?
It's probably not or at least it wasn't tested with 16.1.
Did you modify the design from hdl_2016_r2 or the default design fails ?