Can anybody help me by providing reference code to prove my design.
FPGA:- ZC706 board with AD9172.
The project can be found here: https://github.com/analogdevicesinc/hdl/tree/master/projects/dac_fmc_ebz/zc706 and documentation here: https://wiki.analog.com/resources/eval/user-guides/ad-dac-fmc-ebz
The sampling rate per data stream is 368 Msps for the default configuration. The HDL needs to be rebuild for other use cases in order to be able have a larger bandwidth.
The maximum complex datarate for the AD9172 is 1.54GSPS so you won't be able to generate a 2GHz signal only from the data transmitted from the FPGA, but you'll need to use the AD9172 NCO. For further details please see:
DO you mean we need to configure the NCO using SPI?
One option is to configure the NCO, if the maximum data rate from the FPGA is ok with you, or reconfigure the HDL project to a different mode and modify the software project accordingly.
We have build the HDL Project for JESD MODE 18 and 20.
Can you please tell me where to modify in the software project and related clocks for JESD MODE 18 and 20.
A branch with mode 20 configuration can be found here:
Can you please send the code for VC707 Evaluation board.
We don't have support for VC707. You could do the port yourself using https://wiki.analog.com/resources/fpga/docs/hdl/porting_project_quick_start_guide
We are getting DAC output from 500MHz to 2GHz using MODE 20.
Now i want to generate modulated signal.
Where is the data corresponding for the required frequency is generated in code? (by using CORDIC or DDS)
I've missed your reply. Please open new threads with new questions.
Your question is related to the DDS HDL implementation ? Or No-OS code ?