Can anybody help me by providing reference code to prove my design.
FPGA:- ZC706 board with AD9172.
Hi Cristian Pop,
Could you please send me your E-mail ID, so that i can share the .hdf file.
Please use the "Insert->Insert image/video/file" menu to upload the file
i am getting like above message after uploading.
The project can be found here: https://github.com/analogdevicesinc/hdl/tree/master/projects/dac_fmc_ebz/zc706 and documentation here: https://wiki.analog.com/resources/eval/user-guides/ad-dac-fmc-ebz
Please change the extension .txt to .hdf
What revision of the ZC706 board are you using ? Did you change the default VADJ settings of 2.5V to other voltage ?
It seems to be working with your hdf file.
As per the reference design what are the clock outputs to be monitor.
As per the configuration ofHMC7044 we are getting 368.64 MHz(CLOCKOUT 2, 12), 5.72 MHz at(CLOCKOUT 3,13) .
pll2_freq = 2949120000
for outputs 2 and 12 divider = 8 => 2949120000 / 8 = 368640000
for outputs 3 and 13 divider = 512 => 2949120000 / 512 = 5760000
Can you please explain how we are measuring Link clock?
Link clock is measured as a ratio against the system clock, which by default is 100MHz. Exact implementation of the measuring module can be found here: https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_clock_mon.v .
You can also check Clock monitor section from: wiki.analog.com/.../axi_jesd204_tx