JESD204B COMMUNICATION WITH AD9172.

byreddy1029@gmail.com on Jul 16, 2019

Can anybody help me by providing reference code to prove my design.

FPGA:- ZC706 board with AD9172.

Regards,

Rajasekhar reddy.

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byreddy1029@gmail.com Jul 16, 2019 in reply to CristianPop +1

Hi Cristian Pop,

Could you please send me your E-mail ID, so that i can share the .hdf file.
CristianPop
Jul 16, 2019 in reply to byreddy1029@gmail.com +1
Please use the "Insert->Insert image/video/file" menu to upload the file
byreddy1029@gmail.com Jul 16, 2019 in reply to CristianPop +1

i am getting like above message after uploading.

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0 AdrianC

on Jul 16, 2019 6:44 AM over 2 years ago
Hello,

The project can be found here: https://github.com/analogdevicesinc/hdl/tree/master/projects/dac_fmc_ebz/zc706 and documentation here: https://wiki.analog.com/resources/eval/user-guides/ad-dac-fmc-ebz

Regards,

Adrian
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0 byreddy1029@gmail.com on Jul 16, 2019 7:18 AM over 2 years ago in reply to AdrianC

We have loaded all the drivers related to SDK platform for JESD (.c & .h files), we are able to configure the AD9172 eval board (ie related clocks for PLL and DAC are coming) with ZC706 FPGA Board.

The Clocks,Chip ID, PLL Lock are configured but the 40 MHz DAC output is not visible.The related print statements with the output from DAC are printed on the RS232 (Tera Term screen shot attached) but we are not able see any output from AD9172 Eval. Board.
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0 byreddy1029@gmail.com on Jul 16, 2019 9:05 AM over 2 years ago in reply to CristianPop

Hi Cristian Pop,

Could you please send me your E-mail ID, so that i can share the .hdf file.
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0 CristianPop

on Jul 16, 2019 9:14 AM over 2 years ago in reply to byreddy1029@gmail.com
Please use the "Insert->Insert image/video/file" menu to upload the file
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0 byreddy1029@gmail.com on Jul 16, 2019 9:17 AM over 2 years ago in reply to CristianPop
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0 byreddy1029@gmail.com on Jul 16, 2019 9:19 AM over 2 years ago in reply to CristianPop

i am getting like above message after uploading.
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0 byreddy1029@gmail.com on Jul 16, 2019 9:21 AM over 2 years ago in reply to CristianPop

system.txt

Please change the extension .txt to .hdf
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0 byreddy1029@gmail.com on Jul 16, 2019 9:21 AM over 2 years ago in reply to CristianPop

system.txt

Please change the extension .txt to .hdf
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0 AdrianC

on Jul 16, 2019 9:57 AM over 2 years ago in reply to byreddy1029@gmail.com
Hello,

What revision of the ZC706 board are you using ? Did you change the default VADJ settings of 2.5V to other voltage ?

Regards,

Adrian
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0 CristianPop

on Jul 16, 2019 10:01 AM over 2 years ago in reply to byreddy1029@gmail.com
It seems to be working with your hdf file.
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0 byreddy1029@gmail.com on Jul 16, 2019 10:09 AM over 2 years ago in reply to AdrianC

We are using ZC706 version2.0.

VADJ is 2.5V as default.
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0 byreddy1029@gmail.com on Jul 16, 2019 10:20 AM over 2 years ago in reply to CristianPop

Hi,

As per the reference design what are the clock outputs to be monitor.

As per the configuration ofHMC7044 we are getting 368.64 MHz(CLOCKOUT 2, 12), 5.72 MHz at(CLOCKOUT 3,13) .
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0 CristianPop

on Jul 16, 2019 10:29 AM over 2 years ago in reply to byreddy1029@gmail.com
Hello,

pll2_freq = 2949120000

for outputs 2 and 12 divider = 8 => 2949120000 / 8 = 368640000

for outputs 3 and 13 divider = 512 => 2949120000 / 512 = 5760000
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