why do you use 3 separate axi_clkgen_v1_0 IP cores?

Is there a reason to use 3 separate  axi_clkgen_v1_0 IP cores instead of 1? My Tx and Rx clock are working on the same sample rate. And if I compare the settings of the 3 IP cores, they are all the same.

Can I simple remove 2 IP's, and share one clock? Does the Talise package allow this?