Is there a reason to use 3 separate axi_clkgen_v1_0 IP cores instead of 1? My Tx and Rx clock are working on the same sample rate. And if I compare the settings of the 3 IP cores, they are all the same.
Can I simple remove 2 IP's, and share one clock? Does the Talise package allow this?
moving to FPGA subspace
Hi,The 3 are there to support different sampling rates on the 3 paths, Rx, Rx_obs and Tx.If you plan to go with fixed rates, you can. You have to change the hdl and software.But keep in mid that the Tx has 4 lanes the Rx and Rx_obs each have 2.Andrei
Change the hdl is no problem for me. But could you point me to the right direction, where i should change the software?
Are you using linux or no-OS?
linux,using the master branch.