I am using adrv9009 No-os design using vivado 2018.3 on zcu102 board. I want to create a loop back i.e. transmitting data through DAC and receive it back from ADC.
For testing the loop back I am sending the DC signal to DAC in all four channels, but jesd_tx output is struck at "bcbcbcbc" in all the four channels.
ILA at input of the jesd_tx
ILA at the output of the jesd_tx for single channel
On the terminal, jesd_tx status shows CGS as link status.
I think to transmit signal to DAC the link status should to DATA as in rx_jesd and rx_os_jesd.
How to change the link status to DATA ?
Should it done in hardware or software ?
What branches of HDL/NO-OS are you using ?
It appears the the JESD204B link is not up for the TX path, that's why you receive the BC values.
Have you done modifications in HDL ? Does your system work correctly without any software modifications ?
I am the using the latest branch available on Github.
I have rectified the problem, actually I had placed ILA in the data path inappropriately, due to which state machine was stuck at CGS state.
Now my state machine goes into DATA mode and I can verify it at UART terminal, but received DATA from ADC is still not matching the DATA transmitted to DAC.
Does this design support DC signal?
You cannot transmit DC signals over the air(or cable), you need to transmit I/Q paired data. Even if you transmit the data, it won't be exactly the same (bit-to-bit) as it goes through several processing blocks on both the output path and the input path.
What do you mean by I/Q paired data ?
What is the range of the input frequency we can transmit ?
Some exaplaination of IQ paired data: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/math
You can probably send DC data as baseband signal and you should see the LO at which the part is configured and at reception you'll see noise.