How to use FPGA to driver 2 AD9371, the Tx channel and Rx channel

We use FPGA XC7Z045 to drive multiple AD9371 chips. I copy the most of the design for the second chip.

After finishing adding the second AD9371 design block, I found that the TX of the first AD9371 (which is working normally before adding the second AD9371 design)

is failed to using. The block of DDR design is followed:

When using the 2 AD9371 chips as the picture shown, the Transmitte IQ data  of RF port is as followed:

However, if we remove the AXI Interface and conncet the axi_dacfifo 2 to a unsed Pin , The Transmitted IQ data of RF port is normal :

Therefore, How should I use thse two  axi_dac_fifo at the same time to operate the DDR to transmit different data to these two Ad9371