We use FPGA XC7Z045 to drive multiple AD9371 chips. I copy the most of the design for the second chip.
After finishing adding the second AD9371 design block, I found that the TX of the first AD9371 (which is working normally before adding the second AD9371 design)
is failed to using. The block of DDR design is followed:
When using the 2 AD9371 chips as the picture shown, the Transmitte IQ data of RF port is as followed:
However, if we remove the AXI Interface and conncet the axi_dacfifo 2 to a unsed Pin , The Transmitted IQ data of RF port is normal :
Therefore, How should I use thse two axi_dac_fifo at the same time to operate the DDR to transmit different data to these two Ad9371
I cannot say, as I haven't tested the design in this configuration. Maybe both FIFOs overwrite the same memory space ?
In our designs we used a single AXI_DAC_FIFO to connect multiple TX IPs: e.g https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9009_zu11eg_som by increasing the DAC_DATA_WIDTH parameter. The linked design has two ADRV9009 which have a similar interface with AD9371.
Is this something you could do in your design ?
OK, I am downloading this example now. My design is as below, I wonder why it fails to work.
It will definitly owerwrite the same memory space. You should use one single axi_dacfifo, and merge the various data sources with a upack module, as AdrianC suggested.