Problem with the Simulation of the IP core AXI_AD7616, unable to write to the cmd or sdo fifo

Hi everyone! I would like to design in Vivado a custom AXI master to control the IP core "axi_ad7616" from ADI (https://wiki.analog.com/resources/fpga/docs/axi_ad7616). In the final project, I need to interface the ADC AD7616 with my Artix 7 FPGA using the SPI bus (serial mode). 

As a first step, I've decided to do a simulation just of the IP core to better understand its behaviour, therefore I have instantiated the component and prepared the attached testbench.vhd

In this simulation, my idea was to perform some register READ/WRITE operations in order to produce the desired output waveform from SDO. Unfortunately, as you can see from the waveforms below, I was not even able to write to the cmd_fifo or sdo_fifo. In the pictures, sdo_fifo_room and cmd_fifo_room are plotted and their values (representing the number of free entries in the FIFO) do not change after the WRITE operation. Instead, read/write operations to different registers (enable, reg_up_cntrl...) seem to be correctly performed.

Do you have any idea why is not working? An example of using this kind of ADI IP core or more documentation/link are also very appreciated.

The Register Maps I have used are reported here https://wiki.analog.com/resources/fpga/docs/axi_ad7616 and here https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi#register_map.

Thanks,

Andrea

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/12/2019 06:23:38 PM
-- Design Name: 
-- Module Name: topsource_simul_ad7616 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity topsource_simul_ad7616_TB is
--qui non mettere niente, se ci sono degli ingressi e uscite poi non si possono pilotare "dall'interno"
end topsource_simul_ad7616_TB;

architecture Behavior of topsource_simul_ad7616_TB is
COMPONENT axi_ad7616_0
  PORT (
    rx_sclk : OUT STD_LOGIC;
    rx_cs_n : OUT STD_LOGIC;
    rx_sdo : OUT STD_LOGIC;
    rx_sdi_0 : IN STD_LOGIC;
    rx_sdi_1 : IN STD_LOGIC;
    rx_db_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    rx_db_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    rx_db_t : OUT STD_LOGIC;
    rx_rd_n : OUT STD_LOGIC;
    rx_wr_n : OUT STD_LOGIC;
    rx_cnvst : OUT STD_LOGIC;
    rx_busy : IN STD_LOGIC;
    s_axi_aclk : IN STD_LOGIC;
    s_axi_aresetn : IN STD_LOGIC;
    s_axi_awvalid : IN STD_LOGIC;
    s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    s_axi_awready : OUT STD_LOGIC;
    s_axi_wvalid : IN STD_LOGIC;
    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    s_axi_wready : OUT STD_LOGIC;
    s_axi_bvalid : OUT STD_LOGIC;
    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_bready : IN STD_LOGIC;
    s_axi_arvalid : IN STD_LOGIC;
    s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    s_axi_arready : OUT STD_LOGIC;
    s_axi_rvalid : OUT STD_LOGIC;
    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_rready : IN STD_LOGIC;
    adc_valid : OUT STD_LOGIC;
    adc_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    adc_sync : OUT STD_LOGIC;
    irq : OUT STD_LOGIC
  );
END COMPONENT;
     
            signal      rx_sclk_0 :        STD_LOGIC;
            signal      rx_cs_n_0 :        STD_LOGIC;
            signal      rx_sdo_0 :         STD_LOGIC;
            signal      rx_sdi_0_0 :       STD_LOGIC :='0';
            signal      rx_sdi_1_0 :       STD_LOGIC :='0';
            signal      rx_db_o_0 :        STD_LOGIC_VECTOR(15 DOWNTO 0);
            signal      rx_db_i_0 :        STD_LOGIC_VECTOR(15 DOWNTO 0) :=x"0000";
            signal      rx_db_t_0 :        STD_LOGIC :='0';
            signal      rx_rd_n_0 :        STD_LOGIC;
            signal      rx_wr_n_0 :        STD_LOGIC;
            signal      rx_cnvst_0 :       STD_LOGIC;
            signal      rx_busy_0 :        STD_LOGIC :='0';
            signal      s_axi_aclk_0 :     STD_LOGIC;
            signal      s_axi_aresetn_0 :  STD_LOGIC := '1';
            signal      s_axi_awvalid_0 :  STD_LOGIC :='0';
            signal      s_axi_awaddr_0 :   STD_LOGIC_VECTOR(15 DOWNTO 0) :=x"0000";
            signal      s_axi_awprot_0 :   STD_LOGIC_VECTOR(2 DOWNTO 0) :=b"000";
            signal      s_axi_awready_0 :  STD_LOGIC;
            signal      s_axi_wvalid_0 :   STD_LOGIC :='0';
            signal      s_axi_wdata_0 :    STD_LOGIC_VECTOR(31 DOWNTO 0) :=x"00000000";
            signal      s_axi_wstrb_0 :    STD_LOGIC_VECTOR(3 DOWNTO 0) :=x"f";
            signal      s_axi_wready_0 :   STD_LOGIC;
            signal      s_axi_bvalid_0 :   STD_LOGIC;
            signal      s_axi_bresp_0 :    STD_LOGIC_VECTOR(1 DOWNTO 0);
            signal      s_axi_bready_0 :   STD_LOGIC :='1';
            signal      s_axi_arvalid_0 :  STD_LOGIC :='0';
            signal      s_axi_araddr_0 :   STD_LOGIC_VECTOR(15 DOWNTO 0):=x"0000";
            signal      s_axi_arprot_0 :   STD_LOGIC_VECTOR(2 DOWNTO 0):=b"000";
            signal      s_axi_arready_0 :  STD_LOGIC;
            signal      s_axi_rvalid_0 :   STD_LOGIC;
            signal      s_axi_rresp_0 :    STD_LOGIC_VECTOR(1 DOWNTO 0);
            signal      s_axi_rdata_0 :    STD_LOGIC_VECTOR(31 DOWNTO 0);
            signal      s_axi_rready_0 :   STD_LOGIC :='1';
            signal      adc_valid_0 :      STD_LOGIC;
            signal      adc_data_0 :       STD_LOGIC_VECTOR(15 DOWNTO 0);
            signal      adc_sync_0 :       STD_LOGIC;
            signal      irq_0 :            STD_LOGIC;          
  
            -- Clock period definitions
            constant clk_period : time := 25 ns;
   
begin
instance_ad7616_0 : axi_ad7616_0
  PORT MAP (
    rx_sclk => rx_sclk_0,
    rx_cs_n => rx_cs_n_0,
    rx_sdo => rx_sdo_0,
    rx_sdi_0 => rx_sdi_0_0,
    rx_sdi_1 => rx_sdi_1_0,
    rx_db_o => rx_db_o_0,
    rx_db_i => rx_db_i_0,
    rx_db_t => rx_db_t_0,
    rx_rd_n => rx_rd_n_0,
    rx_wr_n => rx_wr_n_0,
    rx_cnvst => rx_cnvst_0,
    rx_busy => rx_busy_0,
    s_axi_aclk => s_axi_aclk_0,
    s_axi_aresetn => s_axi_aresetn_0,
    s_axi_awvalid => s_axi_awvalid_0,
    s_axi_awaddr => s_axi_awaddr_0,
    s_axi_awprot => s_axi_awprot_0,
    s_axi_awready => s_axi_awready_0,
    s_axi_wvalid => s_axi_wvalid_0,
    s_axi_wdata => s_axi_wdata_0,
    s_axi_wstrb => s_axi_wstrb_0,
    s_axi_wready => s_axi_wready_0,
    s_axi_bvalid => s_axi_bvalid_0,
    s_axi_bresp => s_axi_bresp_0,
    s_axi_bready => s_axi_bready_0,
    s_axi_arvalid => s_axi_arvalid_0,
    s_axi_araddr => s_axi_araddr_0,
    s_axi_arprot => s_axi_arprot_0,
    s_axi_arready => s_axi_arready_0,
    s_axi_rvalid => s_axi_rvalid_0,
    s_axi_rresp => s_axi_rresp_0,
    s_axi_rdata => s_axi_rdata_0,
    s_axi_rready => s_axi_rready_0,
    adc_valid => adc_valid_0,
    adc_data => adc_data_0,
    adc_sync => adc_sync_0,
    irq => irq_0
  );

   -- Clock process definitions
   clk_process :process
   begin
		s_axi_aclk_0 <= '0';
		wait for clk_period/2;
		s_axi_aclk_0 <= '1';
		wait for clk_period/2;
   end process;

   -- datain_process: process(clk)
   -- begin
   --  if rising_edge(clk) then
   --    data_from_adc <= not data_from_adc;
   --  end if;
   -- end process; 

   -- Stimulus process
   stim_proc: process
   begin		
        -- reset
        wait for 50 ns;	
        s_axi_aresetn_0 <= '0';        
        wait for clk_period;
        s_axi_aresetn_0 <= '1';
        
        --read 
        wait for clk_period;
        s_axi_araddr_0 <= x"0000";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period; 
        
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0040";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;
        
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0100";
        wait for clk_period;
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period; 
        
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0400";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;  
        
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0100";
        wait for clk_period;
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;      
       
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0108";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;
        
                
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0440";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;
        
            
        --write
        wait for clk_period;
        s_axi_awaddr_0 <= x"0100";
        s_axi_wdata_0 <= x"00000001";
        s_axi_bready_0 <= '1';
        --wait for clk_period;
        s_axi_awvalid_0 <= '1'; 
        s_axi_wvalid_0 <= '1';      
        wait until (rising_edge(s_axi_awready_0) and rising_edge(s_axi_wready_0)); 
        wait until rising_edge(s_axi_bvalid_0); 
        s_axi_awvalid_0 <= '0';
        s_axi_wvalid_0 <= '0';
        s_axi_bready_0 <= '0';           
        wait for clk_period;
        
        
        --write
        wait for clk_period;
        s_axi_awaddr_0 <= x"0440";
        s_axi_wdata_0 <= x"00000003";
        s_axi_bready_0 <= '1';
        --wait for clk_period;
        s_axi_awvalid_0 <= '1'; 
        s_axi_wvalid_0 <= '1';      
        wait until (rising_edge(s_axi_awready_0) and rising_edge(s_axi_wready_0)); 
        wait until rising_edge(s_axi_bvalid_0); 
        s_axi_awvalid_0 <= '0';
        s_axi_wvalid_0 <= '0';
        s_axi_bready_0 <= '0';           
        wait for clk_period;
        
        --write
        wait for clk_period;
        s_axi_awaddr_0 <= x"0040";
        s_axi_wdata_0 <= x"00000001";
        s_axi_bready_0 <= '1';
        --wait for clk_period;
        s_axi_awvalid_0 <= '1'; 
        s_axi_wvalid_0 <= '1';      
        wait until (rising_edge(s_axi_awready_0) and rising_edge(s_axi_wready_0)); 
        wait until rising_edge(s_axi_bvalid_0); 
        s_axi_awvalid_0 <= '0';
        s_axi_wvalid_0 <= '0';
        s_axi_bready_0 <= '0';           
        wait for clk_period;
        
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0100";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;      
       
       
        --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0440";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;
        
         --read 
        wait for clk_period*4;
        s_axi_araddr_0 <= x"0040";
        s_axi_arvalid_0 <= '1';
        s_axi_rready_0 <= '1';       
        wait until rising_edge(s_axi_arready_0);  --wait the receiver to be ready
        s_axi_arvalid_0 <= '0';       
        wait until rising_edge(s_axi_rvalid_0);   --wait the data from the receiver
        s_axi_rready_0 <= '0'; 
        wait for clk_period;
              
               
        --write
        wait for clk_period;
        s_axi_awaddr_0 <= x"00e0";
        s_axi_wdata_0 <= x"00000001";
        s_axi_bready_0 <= '1';
        --wait for clk_period;
        s_axi_awvalid_0 <= '1'; 
        s_axi_wvalid_0 <= '1';      
        wait until (rising_edge(s_axi_awready_0) and rising_edge(s_axi_wready_0)); 
        wait until rising_edge(s_axi_bvalid_0);
        s_axi_awvalid_0 <= '0';
        s_axi_wvalid_0 <= '0';
        s_axi_bready_0 <= '0';           
        wait for clk_period;
        
        --write
        wait for clk_period;
        s_axi_awaddr_0 <= x"00e4";
        s_axi_wdata_0 <= x"00000001";
        s_axi_bready_0 <= '1';
        --wait for clk_period;
        s_axi_awvalid_0 <= '1'; 
        s_axi_wvalid_0 <= '1';      
        wait until (rising_edge(s_axi_awready_0) and rising_edge(s_axi_wready_0)); 
        wait until rising_edge(s_axi_bvalid_0);
        s_axi_awvalid_0 <= '0';
        s_axi_wvalid_0 <= '0';
        s_axi_bready_0 <= '0';           
        wait for clk_period;
          
  
      wait;   --wait forever
   end process;
   
end Behavior;