Hi FPGA experts:
I am using AD9361 ip core in my custom board. I debug the signals about ad9361 when tx pkg. The behavior of dac_valid_i0 and dac_enable_i0 seems strange. They always be 1:
Could you give some advice about what is going wrong?Thanks
Hi,What git branch and OS are you using(Linux, no-OS)?Can you read the DAC common REG_RATECNTRL(0x004c) register?https://wiki.analog.com/resources/fpga/docs/axi_ad9361
Thanks for your reply. I am using no-os:https://github.com/analogdevicesinc/no-OS/tree/2016_R2/ad9361
I read DAC common REG_RATECNTRL(0x004c) register, its value is 0. I think the value is right, because we are using 1R1T CMOS mode. Dose this matters?
Thanks. Looking forward to your reply.
Why are you using such an old release? We recommend using the latest release. Yes, it matters
That register controls a counter that generates the valid signal.
In 1R1T mode, at DDR, CMOS interface the valid will always be high.If you are using an AD9361 with the above interface but in 2R2T mode, the valid will be high once every 2 clock cycles.You can find more info in UG-570 - AD9361 Reference manual - DIGITAL INTERFACE SPECIFICATION(page 90)Andrei
Thanks a lot. The single_data_rate_enable parameter in default_init_param is set to 0, I think I am using 1R1T, DDR, CMOS mode. So the valid will always be high. Am I right?
Thanks a lot.
Yes, that is right. Andrei
Thanks a lot. I got it now. Have a nice day!