I want to know about the data of ad9361 collected by adc_capture. Now I add a DMA IP core to the PL side to read and write DDR data. The data read by DMA is FFT transformed on the PL side and then transmitted back to DDR or displayed on the PL side.
I had a problem. For the data of ad9361 collected by adc_capture, I learned two ways of FFT transform on PL side. The first way is to call the FFT IP core of vivado directly. The second way is to use the real FFT project mentioned in the reference ug871-vivado-high-level-synthesis-tutorial (mainly real2xfft and xfft2real in engineering). In real FFT, the combination of IP nuclear energy can be applied to data collected by adc_capture.
Should I change the format of data collected by adc_capture before FFT transform in sdk?
Sorry, but you're so far from the initial state of the reference design, that we can not help with this. Will leave this thread open for a couple of day, if somebody from the team has an opinion about your issue he/she can share it with you. I can not do more than that.
Thanks for your understanding,
Let me change the question. I use adc_capture (16384, ADC_DDR_BASEADDR) to capture the signal. This 16348 should be the number of sampling points. Where is the sampling rate of ADC of the signal I receive? I think I need to know or modify these parameters to do fft.
OK, this is a better question.
By default, the no-OS reference design uses a 30.72MHz sampling rate, with a 18MHz band width. (See here the clock tree and bandwidth and here you can find what represents each number in the clock tree structure) All these numbers will be written into registers of the AD9361. You can modify the init structure of the reference design, or use the API functions to change these values. If you are changing the sampling rates and/or bandwidth you should change the FIR filters configuration too. Check out the Filter Wizard in the FMCOMMS2 User Guide.
The last number in the clock tree will give you the data rate in the data path, inside the HDL design. If all channels are active and you're using LVDS, the clock rate on the path will be 4x of the data rate. These means that the axi_ad9361/l_clk will have a frequency of 122.88MHz by default, but you will have a valid data only on each 4th clock cycle. The main function of the util_rfifo/util_wfifo is to eliminate this difference the reduce the clock rate to the level of the data rate. So, after the FIFOs, you will have a 30.72MHz clock rate (util_ad9361_diclk/clk_out), which will be equal to the data rate. You should try to integrate you FFT after these FIFOs.
Hope this helps,
Filter Wizard in the FMCOMMS2 User Guide is the filter design tool used in matlab?
There are still some unclear points. The signal collected by AD9361 is a mixed Q-channel I-channel signal. If the above method is used to add FFT after Util ffifo/Util ffifo, do you need to add a window function before FFT to specify the length of the received signal and change the timing of the received signal? (Because I think the signal received by AD9361 is real-time, and the signal in the DDR of PS is only a limited sampling point).
If so, why not introduce a DMA loop in the idle HP port for FFT conversion of the sampled signal?
In my understanding it's a good practice to use some windowing function, in order to reduce spectral leakage.
I'm not sure if I understand your question about the DMA. Maybe try to elaborate it.
I'm also adding travisfcollins, he's our signal processing expert.