AXI_AD9361 Data Format

Hello,

We are using the ADRV9361-Z7035 with the FMC carrier in LVDS mode. We are trying to insert a custom IP block between the AXI_AD9361 and the adjacent FIFO IP blocks that performs RX to TX loopback with a user-controlled phase shift. Our custom IP block accepts adc_data_i0 and adc_data_q0 and returns the phase-shifted I/Q samples to dac_data_i0 and dac_data_q0. It is my understanding that by default, adc_data_* is 12-bit 2's compliment sign-extended to 16-bits and dac_data_* is 16-bit 2's compliment where only the upper 12 bits are used by the AXI_AD9361 core. However, it appears that when our IP block writes negative values to dac_data_* the AD9361 interface can't handle the data format.

As a quick example, suppose the incoming I/Q sample from AXI_AD9361 is (1000,0) and we phase shift it by 180 degrees. Only focusing on the I-component...

adc_data_i0 = +1000 or 0x03e8

180 degree phase shift results in -1000 or 0xfc18

and dac_data_i0 gets 0xc180 (left shifted by 4 bits)

1. Is this the correct understanding of how the 16-bit I/Q samples get read and written to the AXI_AD9361 block?

2. Can you confirm the following for RX and TX paths? 

        RX: LVDS -> 12 bit offset binary -> 16 bit 2's compliment

        TX: 16 bit 2's compliment -> 12 bit 2's compliment (top 12 bits) -> LVDS

3. For the built-in RX -> TX loopback, can you confirm that the 48-bit "adc_data" loopback signal always contains 12-bit offset binary?

Thanks,

Glen