I have modified the kcu105 no os project to configure fmc-daq3 on ZCU102, after many changes, finally the board has been run successfully, and the adc works. I put the adc to test mode and captured data correctly, however when I connect a B200 (ettus USRP) TX to the RX input, the signal is not clean and seems to be saturated. the freq I have captured is shifted about 6 MHz and many spurs and undesired dc is appeared.
the signal should be in 430MHz but it is in 436.5 MHz.
did the configuration procedure go wrong?
could anyone help me to find out the problem?
When plotting the data, what sampling frequency did you use ?
By default the system runs at 1233Msps, most likely this creates the issue with the incorrectly detected input frequency.
that's right. it will be OK by setting the rate 1233MHz. but I need 1250 MHz rate. when I change the related parameters in Microblaze to 1250MHz the ad9680 PLL (also ad9152) could not be locked.
For AD9152 maximum lane rate is 12.38 Gbps, so you won't be able to go to 12.5Gbps, that's why we chose 12.33Gbps as default.
I am still have trouble with ad9152. there is nothing at the output. I put a 4 lane dds to create signal and inject it to the AXI_ad9152_core. but there is nothing using B200 for receiving. (Also I have put it in loopback mode to see it by the ad9680). the microblaze code did not generate any errors and it configured it successfully.
Using the B200 includes additional complexity, let's initially check if loopback works. There is an DDS inside of the AD9152 IP. Does that work ?
In order to send the data from the dac_ddata_x buses, the axi_ad9152 should be configured for each channel to output input data (register 0x418 set to 2, https://wiki.analog.com/resources/fpga/docs/hdl/regmap DAC_CHANNEL section). Have you set that up ? Also, the input data should be generated on the tx_clk/dac_clk.
Thank you, I did not know that the ad9152 core contains dds.
I found that I did not change some blocks to be compatible with zcu102, they were still configured for kcu105, and xcvr type was GTHE3, after changing them to GTHE4 and other chenges, it was fixed. the default code let internal dds to go out, so the first thing I saw after running the code was a 33.1MHz signal which is configured by default, I set that to let my dds go out. it works with 1233 sampling rate.