Goal: I want to send certain frequency at TX and disable RX on my custom logic.
I have implemented a logic and i want to send the frequency of DDS according to my logic. Further I want to disable the RX according to my logic. I have seen both these functionalities from IIO-Osc, but i couldn't figure out how to do this from HDL design.
I also tried to use xilinx DDS and send it's generated frequency on TX path but i'm still stuck in matching clocks. Because my HDL design is running at 100MHz and TX data rate is different (set from IIO-Osc).
what project are you working on (carrier + fmc board), please share the git location of the project.
In general, each project that has a DAC includes a DDS in the HDL. For JESD based converters this is located in the transport layer, see https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac while for LVDS interfaces in components with the following format axi_'dacname' e.g. axi_ad9361
For ad9361 the DDS modules are instantiated here: https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_tx_channel.v
As you can see the DDS modules have a control interface which are connected to AXI registers that are programmed from IIO scope ultimately.
You can take the same DDS core and do a HDL control based on your logic.
Sorry i was on leave.
I'm using adrv9361Z7035 with adrv1crr-fmc carrier board and this project https://github.com/analogdevicesinc/hdl/tree/adrv9361z7035_ccfmc_util_axis_fifo_rx_example
I'm stuck in clock domain crossing of my logic and tx dds. In this thread https://ez.analog.com/fpga/f/q-a/106405/how-to-exchange-reg-in-different-clock-domain/314966#314966 Andrei said that up_xfer_cntr is used for clock domain crossing in this project. I searched for documentation but couldn't find. Can u share any documentation on clock domain crossing in this project? or IP core documentation. (DDS and up_xfer_cntrl)
Hi, posting this snap here so that background of this issue is cleared.
This is the output i got at TX when i connected xilinx DDS to dac i and q channel of axi_ad9361. My dds is running at 245.76 MHz so is the data rate. what i got at TX is LO+DDS_tone and LO-DDS_tone. but this is not the case with adi DDS.
can u please on this issue.
Rocky2018 said: i got at TX is LO+DDS_tone and LO-DDS_tone. but this is not the case with adi DDS
Ok, so with the Xilinx one you get the expected result. So on your implementation of the ADI one, you still get no tones?Can you share your changes in the reference design for the ADI DDS? I'm interested in the code. Andrei
Thanks for reply.
andrei_g said:so with the Xilinx one you get the expected result. So on your implementation of the ADI one, you still get no tones?
No, Adi DDS works perfectly fine. I tune it to certain frequency and it gives the required tone. but xilinx dds gives me two tones, one at LO+freq and other at LO-freq as shown in above image.
For example my LO is 155MHz. I send single tune of +1MHz. Expected output is 156MHz but i got 156MHz and 154 MHz. While adi dds gives correct output as expected at 156MHz. This image shows Xilinx DDS output.
I attached i channel of dds to dac_data_i and q channel to dac_data_q ports of axi_ad9361
what i wanted to ask , How u people managed to get this single tone instead two tones at LO+freq and LO-freq.
Hi,Let's have a few checkpoints:
- The maximum sampling rate of the axi_ad9361 is 61.44Mhz (on each channel). The interface clock is sampling_rate*4 (not always 245.76M). So your DDS must be run on a clock generated from the interface clock.- There must be a 90 degree offset between the I and Q signals.I see a mistake in one of my statements above. The expected Tx data is on 16 bits, but not 12 bits sign extended. The Tx takes the first 12MSB and disregards the last 4 bits. The 12bit sign-extended data is on the RX side. Sorry about the confusion.Andrei
My sampling rate is 61.44 MHz so my dds system clock (interface clock) should be 245.76 MHz and IQ sample have 90 degree offset.
andrei_g said:The expected Tx data is on 16 bits, but not 12 bits sign extended. The Tx takes the first 12MSB and disregards the last 4 bits
Thank you very much for clearing this. I was supplying 12 bit sign extended data to the dac port. let me fix this and i'll update here.
Hi,Just to be clear, the idea is that the interface runs at 245.76M, not the DDS core. The DDS should generate samples at 61.44.Andrei
here are my findings.
Third, I added xilinx DDS which provides I/Q data and connected them to axi_ad9361 dac_i0 and dac_q0 channel. (previously, These ports were connected to dac_dma). Then i write 0x2 at 0x418 reg of axi_core register through iio-oscilloscope. DDS tone frequency is 1.44MHz
I also tried to connect in-phase data at both dac_i0 and dac_q0 channels to check if any change but the result doesn't change. ideally i should have got single tone which i connected I/Q data and two tones when i connected in-phase data. but both resulted the same output.
sampling rate=61.44 MHz.
Can u comment on this.
Hi,Have you wrote in the DAC_DDS_SEL[3:0] register for all 4 channels?I will make a setup today or tomorrow to play out with the Xilinx DDS and let you know what I find.
The problems I've seen:- the Xilinx DDS compiler can be configured for 4 channels but not with an independent interface for each channel.- using 4 independent instances of the DDS Compiler can't guarantee that all 4 channels are in syncAs I see you can use some other DDS that can generate synchronized 4 channel data.I can packetize the current ADI DDS and make it a standalone IP. It should not take that long.
The questions is, what is your end goal with the DDS(how do you want o use it)?Do you want to control the frequency on the fly?Andrei
Thank you very much for your input.
andrei_g said:Have you wrote in the DAC_DDS_SEL[3:0] register for all 4 channels?
I just wrote 0x2 to 0x418 register. I was assuming this single register control all the channels. How do i check this register for other channels?
I'm using 2 channels only. Xilinx DDS compiler can generate sin and cos signal at the same time which can be used as I and Q channel. I'm emulating independent I/Q using multiplexers. For in phase signals, I connected sin wave bit to both I and Q channels. For 90 degree phase shift, I connected both sin and cos data to I and Q interface of axi_ad9361 IP.
andrei_g said:The questions is, what is your end goal with the DDS(how do you want o use it)?Do you want to control the frequency on the fly?
yes, I want run time frequency control. Xilinx DDS provides better frequency resolution as compared to adi DDS. I'm using run time configuration option of xilinx DDS.