sending certain frequency at TX based on HDL logic


Goal: I want to send certain frequency at TX and disable RX on my custom logic.  

I have implemented a logic and i want to send the frequency of DDS according to my logic. Further I want to disable the RX according to my logic. I have seen both these functionalities from IIO-Osc, but i couldn't figure out how to do this from HDL design. 

I also tried to use xilinx DDS and send it's generated frequency on TX path but i'm still stuck in matching clocks. Because my HDL design is running at 100MHz and TX data rate is different (set from IIO-Osc). 

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