Goal: I want to send certain frequency at TX and disable RX on my custom logic.
I have implemented a logic and i want to send the frequency of DDS according to my logic. Further I want to disable the RX according to my logic. I have seen both these functionalities from IIO-Osc, but i couldn't figure out how to do this from HDL design.
I also tried to use xilinx DDS and send it's generated frequency on TX path but i'm still stuck in matching clocks. Because my HDL design is running at 100MHz and TX data rate is different (set from IIO-Osc).
what project are you working on (carrier + fmc board), please share the git location of the project.
In general, each project that has a DAC includes a DDS in the HDL. For JESD based converters this is located in the transport layer, see https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac while for LVDS interfaces in components with the following format axi_'dacname' e.g. axi_ad9361
For ad9361 the DDS modules are instantiated here: https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_tx_channel.v
As you can see the DDS modules have a control interface which are connected to AXI registers that are programmed from IIO scope ultimately.
You can take the same DDS core and do a HDL control based on your logic.
Sorry i was on leave.
I'm using adrv9361Z7035 with adrv1crr-fmc carrier board and this project https://github.com/analogdevicesinc/hdl/tree/adrv9361z7035_ccfmc_util_axis_fifo_rx_example
I'm stuck in clock domain crossing of my logic and tx dds. In this thread https://ez.analog.com/fpga/f/q-a/106405/how-to-exchange-reg-in-different-clock-domain/314966#314966 Andrei said that up_xfer_cntr is used for clock domain crossing in this project. I searched for documentation but couldn't find. Can u share any documentation on clock domain crossing in this project? or IP core documentation. (DDS and up_xfer_cntrl)
Hi,We don't have any documentation regarding the clock domain crossing module.up_xfer_cntr is used to pass data from the cpu clock to the dac core clock.100M to 245.71M(max) in this case. The whole module is a fancier flop synchronization. https://zipcpu.com/blog/2017/10/20/cdc.html
We also don't have any documentation on the DDS side, but I can answer your questions regarding the DDS.
Thanks for quick reply. Here are my questions.
Hi,1. You can consider it that way, so yes. The DDS runs on l_clk sampling-rate * 4, but only one in every 4 clock cycles is valid.2. Two's complement format.The DDS is a dual-tone(a summation of 2 DDS modules). For a single tone set both frequencies to the same value. To avoid over-range values when using both, the maximum amplitude is 0x4000 for each tone.
For the phase accumulator part of the DDS, to calculate the frequency control word use:PCW=(f_out * 2^16)/sampling_rate
Actually, the info from the control registers of the DDS applies here. https://wiki.analog.com/resources/fpga/docs/hdl/regmap
Dac Channel -> REG_CHAN_CNDRL_1/2/3/4.