Problem building HDL

Hello!

I am finding my way with HDL design. The goal is to test AD-FMCOMMS3-EBZ on AC701 carrier. As far as I see, project for AC701 carrier was last posted under hdl_2017_r1, which requires Vivado 2016.4. I am doing this on Win7 x64 machine. I have cygwin installed with gnu make.

As per https://wiki.analog.com/resources/fpga/docs/build#clone_the_hdl_repository I have cloned repository and switched to hdl_2017_r1 branch:

$ git status
On branch hdl_2017_r1
Your branch is up to date with 'origin/hdl_2017_r1'.

nothing to commit, working tree clean

Next I navigate to project folder and execute make. At this point I see process started and then just hung.

$ cd ~/adi/hdl/projects/fmcomms2/ac701/

$ make
make -C ../../../library/axi_ad9361
make[1]: Entering directory '/home/victor/adi/hdl/library/axi_ad9361'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
rm: cannot remove 'vivado.log': Device or resource busy
rm: cannot remove 'vivado.jou': Device or resource busy
make[1]: [Makefile:81: axi_ad9361.xpr] Error 1 (ignored)
vivado -mode batch -source axi_ad9361_ip.tcl  >> axi_ad9361_ip.log 2>&1

I see vivado.exe process is taking 170MB of memory and no processor activity. In hdl\library\axi_ad9361\ I see, but reading it does not help me understand the issue. 

axi_ad9361_ip.log
****** Vivado v2016.4 (64-bit)
  **** SW Build 1733598 on Wed Dec 14 22:35:39 MST 2016
  **** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source axi_ad9361_ip.tcl
# source ../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_phdl_dir $ad_hdl_dir
## if [info exists ::env(ADI_HDL_DIR)] {
##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_PHDL_DIR)] {
##   set ad_phdl_dir [file normalize $::env(ADI_PHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip.tcl
## if {![info exists REQUIRED_VIVADO_VERSION]} {
##   set REQUIRED_VIVADO_VERSION "2016.4"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
##   set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
##   set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
## 
##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
##   set f [ipx::add_file $ip_constr_files $proj_filegroup]
##   set_property -dict [list \
##     type ttcl \
##   ] $f
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
##   set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
##   if {$proj_filegroup == {}} {
##     set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
##   }
##   set f [ipx::add_file $ip_bd_files $proj_filegroup]
##   set_property -dict [list \
##     type tclSource \
##   ] $f
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
## 
##   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
## 
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
## 
##   ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
## 
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
##   foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
##     set_property ENABLEMENT_DEPENDENCY $dependency $port
##     if {$driver_value != {}} {
##       set_property DRIVER_VALUE $driver_value $port
##     }
##   }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
##   set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
##   adi_set_ports_dependency $prefix $dependency
## }
## proc adi_add_port_map {bus phys logic} {
##   set map [ipx::add_port_map $phys $bus]
##   set_property "PHYSICAL_NAME" $phys $map
##   set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
##   set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
## 
##   set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
##   set_property "BUS_TYPE_VLNV" $bus_type $bus
##   set_property "INTERFACE_MODE" $mode $bus
## 
##   foreach port_map $port_maps {
##     adi_add_port_map $bus {*}$port_map
##   }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
##   for {set i 0} {$i < 8} {incr i} {
##     set bus_name [format "%s%d" $bus_name_prefix $i]
##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
## 
##     set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
##     set_property "BUS_TYPE_VLNV" $bus_type $bus
##     set_property "INTERFACE_MODE" $mode $bus
## 
##     if {$dependency ne ""} {
##       set bus_dependency [string map [list "{i}" $i] $dependency]
##       set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
##     }
## 
##     foreach port_map $port_maps {
##       lassign $port_map phys logic width
##       set map [ipx::add_port_map $phys $bus]
##       set_property "PHYSICAL_NAME" $phys $map
##       set_property "LOGICAL_NAME" $logic $map
##       set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
##       set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
##     }
##   }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
##   set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
##   set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
##   set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
##   set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
##   set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
##   set_property display_name $clock_inf_name $clock_inf
##   set clock_map [ipx::add_port_map "CLK" $clock_inf]
##   set_property physical_name $clock_signal_name $clock_map
## 
##   set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
##   set_property value $bus_inf_name $assoc_busif
## 
##   if { $reset_signal_name != "" } {
##     set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
##     set_property value $reset_signal_name $assoc_reset
## 
##     set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
##     set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
##     set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
##     set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
##     set_property display_name $reset_inf_name $reset_inf
##     set_property interface_mode $reset_signal_mode $reset_inf
##     set reset_map [ipx::add_port_map "RST" $reset_inf]
##     set_property physical_name $reset_signal_name $reset_map
## 
##     set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
##     if {[string match {*[Nn]} $reset_signal_name] == 1} {
##       set_property value "ACTIVE_LOW" $reset_polarity
##     } else {
##       set_property value "ACTIVE_HIGH" $reset_polarity
##     }
##   }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
##   foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
##     foreach vlnv $vlnvs {
##       ipx::add_subcore $vlnv $file_group
##     }
##   }
## }
## variable ip_constr_files
## proc adi_ip_create {ip_name} {
## 
##   global ad_hdl_dir
##   global ad_phdl_dir
##   global ip_constr_files
##   global REQUIRED_VIVADO_VERSION
##   global IGNORE_VERSION_CHECK
## 
##   set VIVADO_VERSION [version -short]
##   if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
##     puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
##     puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
##     puts -nonewline "got $VIVADO_VERSION.\n"
##   }
## 
##   create_project $ip_name . -force
## 
##   set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
##   set_msg_config -id {IP_Flow 19-2999} -new_severity INFO 
##   set_msg_config -id {IP_Flow 19-1654} -new_severity INFO 
##   set_msg_config -id {IP_Flow 19-4623} -new_severity INFO 
##   set_msg_config -id {IP_Flow 19-459} -new_severity INFO 
## 
##   set ip_constr_files ""
##   set lib_dirs $ad_hdl_dir/library
##   if {$ad_hdl_dir ne $ad_phdl_dir} {
##     lappend lib_dirs $ad_phdl_dir/library
##   }
## 
##   set_property ip_repo_paths $lib_dirs [current_fileset]
##   update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## 
##   global ip_constr_files
## 
##   set ip_constr_files ""
##   foreach m_file $ip_files {
##     if {[file extension $m_file] eq ".xdc"} {
##       lappend ip_constr_files $m_file
##     }
##   }
## 
##   set proj_fileset [get_filesets sources_1]
##   add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
##   set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
## 
##   global ip_constr_files
## 
##   ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##   set_property name $ip_name [ipx::current_core]
##   set_property vendor_display_name {Analog Devices} [ipx::current_core]
##   set_property company_url {www.analog.com} [ipx::current_core]
## 
##   set i_families ""
##   foreach i_part [get_parts] {
##     lappend i_families [get_property FAMILY $i_part]
##   }
##   set i_families [lsort -unique $i_families]
##   set s_families [get_property supported_families [ipx::current_core]]
##   foreach i_family $i_families {
##     set s_families "$s_families $i_family Production"
##     set s_families "$s_families $i_family Beta"
##   }
##   set_property supported_families $s_families [ipx::current_core]
##   ipx::save_core
## 
##   ipx::remove_all_bus_interface [ipx::current_core]
##   set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
##   foreach map $memory_maps {
##     ipx::remove_memory_map [lindex $map 2] [ipx::current_core ]
##   }
##   ipx::save_core
## 
##   set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
##   foreach i_file $ip_constr_files {
##     set i_module [file tail $i_file]
##     regsub {_constr\.xdc} $i_module {} i_module
##     ipx::add_file $i_file $i_filegroup
##     set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup]
##   }
##   ipx::save_core
## }
## proc adi_ip_properties {ip_name} {
## 
##   adi_ip_properties_lite $ip_name
## 
##   ipx::infer_bus_interface {\
##     s_axi_awvalid \
##     s_axi_awaddr \
##     s_axi_awprot \
##     s_axi_awready \
##     s_axi_wvalid \
##     s_axi_wdata \
##     s_axi_wstrb \
##     s_axi_wready \
##     s_axi_bvalid \
##     s_axi_bresp \
##     s_axi_bready \
##     s_axi_arvalid \
##     s_axi_araddr \
##     s_axi_arprot \
##     s_axi_arready \
##     s_axi_rvalid \
##     s_axi_rdata \
##     s_axi_rresp \
##     s_axi_rready} \
##   xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
## 
##   ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
##   ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
## 
##   set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
##   set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
## 
##   if {$raddr_width != $waddr_width} {
##     puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
##     set range 65536
##   } else {
##     if {$raddr_width >= 16} {
##       set range 65536
##     } else {
##       set range [expr 1 << $raddr_width]
##     }
##   }
## 
##   ipx::add_memory_map {s_axi} [ipx::current_core]
##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
##   ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
##   set_property range $range [ipx::get_address_blocks axi_lite \
##     -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
##   ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
##     -of_objects [ipx::current_core]]
##   set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
##     -of_objects [ipx::get_bus_interfaces s_axi_aclk \
##     -of_objects [ipx::current_core]]]
##   ipx::save_core
## }
## proc adi_if_define {name} {
## 
##   ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
##   ipx::create_bus_definition analog.com interface $name 1.0
## 
##   set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
##   set_property xml_file_name ${name}.xml [ipx::current_busdef]
##   set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
## 
##   ipx::save_abstraction_definition [ipx::current_busabs]
##   ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
## 
##   ipx::add_bus_abstraction_port $name [ipx::current_busabs]
##   set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
##   set_property master_presence required $m_intf
##   set_property slave_presence  required $m_intf
##   set_property master_width $width $m_intf
##   set_property slave_width  $width $m_intf
## 
##   set m_dir "in"
##   set s_dir "out"
##   if {$dir eq "output"} {
##     set m_dir "out"
##     set s_dir "in"
##   }
## 
##   set_property master_direction $m_dir $m_intf
##   set_property slave_direction  $s_dir $m_intf
## 
##   if {$type ne "none"} {
##     set_property is_${type} true $m_intf
##   }
## 
##   ipx::save_bus_definition [ipx::current_busdef]
##   ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
## 
##   ipx::add_bus_interface $name [ipx::current_core]
##   set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
##   set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
##   set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
##   set_property interface_mode $mode $m_bus_if
## 
##   foreach map $maps  {
##     set m_maps [regexp -all -inline {\S+} $map]
##     lassign $m_maps p_name p_map
##     ipx::add_port_map $p_name $m_bus_if
##     set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
##   }
## }
# adi_ip_create axi_ad9361
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/cygwin64/home/victor/adi/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/cygwin64/home/victor/adi/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2016.4/data/ip'.
# adi_ip_files axi_ad9361 [list \
#   "$ad_hdl_dir/library/common/ad_rst.v" \
#   "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
#   "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
#   "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \
#   "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
#   "$ad_hdl_dir/library/common/ad_pnmon.v" \
#   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
#   "$ad_hdl_dir/library/common/ad_dds_1.v" \
#   "$ad_hdl_dir/library/common/ad_dds.v" \
#   "$ad_hdl_dir/library/common/ad_datafmt.v" \
#   "$ad_hdl_dir/library/common/ad_dcfilter.v" \
#   "$ad_hdl_dir/library/common/ad_iqcor.v" \
#   "$ad_hdl_dir/library/common/ad_addsub.v" \
#   "$ad_hdl_dir/library/common/ad_tdd_control.v" \
#   "$ad_hdl_dir/library/common/ad_pps_receiver.v" \
#   "$ad_hdl_dir/library/common/up_axi.v" \
#   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
#   "$ad_hdl_dir/library/common/up_xfer_status.v" \
#   "$ad_hdl_dir/library/common/up_clock_mon.v" \
#   "$ad_hdl_dir/library/common/up_delay_cntrl.v" \
#   "$ad_hdl_dir/library/common/up_adc_common.v" \
#   "$ad_hdl_dir/library/common/up_adc_channel.v" \
#   "$ad_hdl_dir/library/common/up_dac_common.v" \
#   "$ad_hdl_dir/library/common/up_dac_channel.v" \
#   "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
#   "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
#   "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" \
#   "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
#   "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
#   "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
#   "axi_ad9361_constr.xdc" \
#   "xilinx/axi_ad9361_lvds_if.v" \
#   "xilinx/axi_ad9361_cmos_if.v" \
#   "axi_ad9361_rx_pnmon.v" \
#   "axi_ad9361_rx_channel.v" \
#   "axi_ad9361_rx.v" \
#   "axi_ad9361_tx_channel.v" \
#   "axi_ad9361_tx.v" \
#   "axi_ad9361_tdd.v" \
#   "axi_ad9361_tdd_if.v" \
#   "axi_ad9361.v" ]
# adi_ip_properties axi_ad9361
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_pnmon.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dds_1.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_xfer_status.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_rst.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dds.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_datafmt.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dcfilter.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_iqcor.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_addsub.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_clock_mon.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_adc_channel.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_dac_channel.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_adc_common.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_dac_common.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_pps_receiver.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_axi.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_pnmon.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dds_1.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_xfer_status.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_rst.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dds.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_datafmt.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_dcfilter.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_iqcor.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_addsub.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_clock_mon.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_adc_channel.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_dac_channel.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_data_in.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/xilinx/common/ad_data_out.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_tdd_control.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_delay_cntrl.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_adc_common.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_dac_common.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_tdd_cntrl.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/ad_pps_receiver.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'D:/cygwin64/home/victor/adi/hdl/library/common/up_axi.v' appears to be outside of the project area 'D:/cygwin64/home/victor/adi/hdl/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-2228] Inferred bus interface 'adc_i0' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'adc_i1' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'adc_q0' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'adc_q1' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'dac_i0' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'dac_i1' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'dac_q0' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'dac_q1' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'rx_in' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'rx_in_n' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'rx_in_p' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'tx_out' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'tx_out_n' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'tx_out_p' of definition 'analog.com:interface:fifo_rd:1.0'.
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_i0" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_i1" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_q0" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_q1" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_i0" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_i1" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface 'dac_in' of definition 'analog.com:interface:fifo_wr:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'dac_out' of definition 'analog.com:interface:fifo_wr:1.0'.
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_q0" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_q1" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "rx_in" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "rx_in_n" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "rx_in_p" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface 'tdd' of definition 'analog.com:interface:fifo_wr:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'tdd_cntr' of definition 'analog.com:interface:fifo_wr:1.0'.
INFO: [IP_Flow 19-2999] Will not infer bus interface "tx_out" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "tx_out_n" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "tx_out_p" for "analog.com:interface:fifo_wr:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_i0" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_i1" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_q0" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "adc_q1" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_i0" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_i1" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_q0" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "dac_q1" for "analog.com:interface:spi_engine_offload_ctrl:1.0". The interface exists with different type "analog.com:interface:fifo_rd:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface 'up' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'rst' as interface 'rst'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 's_axi_aclk' as interface 's_axi_aclk'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'clk' as interface 'clk'.
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'.
INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'gps_pps_irq' as interface 'gps_pps_irq'.
INFO: [IP_Flow 19-4728] Bus Interface 'gps_pps_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'delay_clk' as interface 'delay_clk'.
INFO: [IP_Flow 19-4728] Bus Interface 'delay_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'l_clk' as interface 'l_clk'.
INFO: [IP_Flow 19-4728] Bus Interface 'l_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'.
INFO: [IP_Flow 19-4623] Unrecognized family  qkintexu.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qkintexu.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  virtexues2.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  virtexues2.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 's_axi_aclk' as interface 's_axi_aclk'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
# adi_ip_ttcl axi_ad9361 "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl"
# set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]]
# set_property driver_value 0 [ipx::get_ports *gps_pps* -of_objects [ipx::current_core]]
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \
#   [ipx::get_ports rx_clk_in_p     -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_clk_in_n     -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_frame_in_p   -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_frame_in_n   -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_data_in_p    -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_data_in_n    -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_clk_out_p    -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_clk_out_n    -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_frame_out_p  -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_frame_out_n  -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_data_out_p   -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_data_out_n   -of_objects [ipx::current_core]]
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \
#   [ipx::get_ports rx_clk_in       -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_frame_in     -of_objects [ipx::current_core]] \
#   [ipx::get_ports rx_data_in      -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_clk_out      -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_frame_out    -of_objects [ipx::current_core]] \
#   [ipx::get_ports tx_data_out     -of_objects [ipx::current_core]]
# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
#   -of_objects [ipx::current_core]]
# set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
#   -of_objects [ipx::get_bus_interfaces s_axi_aclk \
#   -of_objects [ipx::current_core]]]
# ipx::save_core [ipx::current_core]

As per https://wiki.analog.com/resources/fpga/docs/build#setup_and_check_your_environment I have appended my .bashrc with

export PATH=$PATH:/cygdrive/d/xilinx/Vivado/2016.4/bin
export PATH=$PATH:/cygdrive/d/xilinx/Vivado_HLS/2016.4/bin
export PATH=$PATH:/cygdrive/d/xilinx/SDK/2016.4/bin
export PATH=$PATH:/cygdrive/d/xilinx/SDK/2016.4/gnu/microblaze/nt/bin
export PATH=$PATH:/cygdrive/d/xilinx/SDK/2016.4/gnu/arm/nt/bin
export PATH=$PATH:/cygdrive/d/xilinx/SDK/2016.4/gnu/microblaze/linux_toolchain/nt64_be/bin
export PATH=$PATH:/cygdrive/d/xilinx/SDK/2016.4/gnu/microblaze/linux_toolchain/nt64_le/bin
export PATH=$PATH:/cygdrive/d/xilinx/SDk/2016.4/gnu/aarch32/nt/gcc-arm-none-eabi/bin

alias xmd=xmd.bat
alias xsct=xsct.bat
alias xsdb=xsdb.bat

I do have Vivado 2016.4 under that path:

D:\>dir /b d:\xilinx\Vivado
2016.4
2018.3

Here are my environment checks

$ which vivado
/cygdrive/d/xilinx/Vivado/2016.4/bin/vivado

$ which make
/usr/bin/make

$ which git
/usr/bin/git

Please help me to trace down the issue.

Thanks in advance