I use FMCADC2 reference design for ZC706 board. It run ok in normal mode ( default mode). Now, i want to change AD9625 to DDC mode(quick config value is 0x82) and get raw I/Q data after "axi_ad9625_core".
I change setting for AD9625 ( as datasheet) via SPI. I change JESD204B core from 8 lane to 2 lane. The data out is still error ( i don't know data arrange before "axi_ad9625_core" and after this)
Below is data out from ILA scope:
It only 2 bus ( one bus is 2 bytes) may be correction data.
Can some one suggest me how to configure reference design to get DDC data.
That FIFO acts more like a buffer, it will save data to the PL_DDR memory after a valid dma_xfer_req, and will start to send data to the DMA after each PL_DDR AXI write burst.
What is your use case? How…