FMCADC2 DDC mode

Hi,

I use FMCADC2 reference design for ZC706 board. It run ok in normal mode ( default mode). Now, i want to change AD9625 to DDC mode(quick config value is 0x82) and get raw I/Q data after "axi_ad9625_core".

I change setting for AD9625 ( as datasheet) via SPI. I change JESD204B core from 8 lane to 2 lane. The data out is still error ( i don't know data arrange before "axi_ad9625_core" and after this)

Below is data out from ILA scope:

It only 2 bus ( one bus is 2 bytes) may be correction data.

Can some one suggest me how to configure reference design to get DDC data.

Thanks you

Parents
  • 0
    •  Analog Employees 
    on May 13, 2019 6:40 AM over 1 year ago

    Hi,

    Did you change anything in the FPGA design? You must reconfigure the whole JESD interface stack, if you want to switch from 8 lanes to 2.

    See this wiki for more info: https://wiki.analog.com/resources/fpga/docs/hdl/generic_jesd_bds

    Thanks,

    -Istvan

  • Dear Istvan,

    This is my Vivado design:

    Axi_ad9625_xcvr:

    util_fmcadc2_xcvr:

    ADI_JESD204_RECEIVE :

    I cannot change axi_ad9625_core, because it fixed every parameter ?

    And this AD9625 settings:

    ad9625_spi_write(dev, 0x05E, 0x82);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x063, 0x8); // single DDC , high bw
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x06E, 0x81); // scrambler - 2 Lane
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x06F, 0x3); //M = 1, S = 4, N' = 16, L = 2, F = 4
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x070, 0x07);//K=8
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    // ad9625_spi_write(dev, 0x072, 0x0F);
    // ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x073, 0x2F);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x131, 102); // NCO = 250
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x132, 0x00);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x0130, 0x03);//ddc gain
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x080, 0xfc);//lane
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ADI_JESD204_Receive settings:

    ad9625_jesd.scramble_enable = 1;
    ad9625_jesd.octets_per_frame = 4;
    ad9625_jesd.frames_per_multiframe = 8;
    ad9625_jesd.subclass_mode = 1;
    ad9625_jesd.sysref_type = INTERN;
    ad9625_jesd.sysref_gpio_pin = GPIO_JESD204_SYSREF;

    I expected that data output order at ADI_JESD204_Receive: I0[N], Q0[N], I0[N+1], Q0[N+1] (LSB to MSB).

    Please help me know data output order at ADI_JESD204_RECEIVE block.

    Thanks you

  • 0
    •  Analog Employees 
    on May 20, 2019 11:05 AM over 1 year ago in reply to ad7960

    Hi ,

    Can you tell me please which operation mode are you targeting (Table 16 from the data sheet), and the sample clock rate that you trying to use?

    Thanks,

    -Istvan

  • Hi Istvan, 

    I use single DDC higbandwidth mode, clock rate is 2.5GHz. Now i read correctly DDC data from FMCADC2, i didn't use axi_ad9625_core. I make other core for get and unpack data from ADI_JESD204_Receive.

    Now i have new problem with axi_ad9625_fifo: this fifo still send data to axi_ad9625_dma core while adc_wr = 0.

    Thanks you for help me. 

    Best regard

  • +1
    •  Analog Employees 
    on May 30, 2019 7:10 AM over 1 year ago in reply to ad7960

    That FIFO acts more like a buffer, it will save data to the PL_DDR memory after a valid dma_xfer_req, and will start to send data to the DMA after each PL_DDR AXI write burst.

    What is your use case? How about your targeted transfer length?

    Thanks,

    -Istvan

  • Hi Istvan,

    "That FIFO acts more like a buffer, it will save data to the PL_DDR memory after a valid dma_xfer_req, and will start to send data to the DMA after each PL_DDR AXI write burst. "  This mean: the saving data to PL_DDR depends on DMA request. If DMA don't request dma_xfer_req, there are no data saved to PL_DDR. That is right?

    We want to save data to PL_DDR and read from this at the same time. 

    Please suggest me how to implement this way?

    Thanks you

    Best regards

Reply
  • Hi Istvan,

    "That FIFO acts more like a buffer, it will save data to the PL_DDR memory after a valid dma_xfer_req, and will start to send data to the DMA after each PL_DDR AXI write burst. "  This mean: the saving data to PL_DDR depends on DMA request. If DMA don't request dma_xfer_req, there are no data saved to PL_DDR. That is right?

    We want to save data to PL_DDR and read from this at the same time. 

    Please suggest me how to implement this way?

    Thanks you

    Best regards

Children
  • 0
    •  Analog Employees 
    on Jun 4, 2019 9:38 AM over 1 year ago in reply to ad7960

    First you have to know  that you can not stream data from ADC to PL_DDR then to PS_DDR, simply because the PS_DDR interface does not have enough bandwidth.

    "We want to save data to PL_DDR and read from this at the same time." - can you tell me what you trying to achieve with this. You want to synchronize the data capture to an external trigger?