FMCADC2 DDC mode

Hi,

I use FMCADC2 reference design for ZC706 board. It run ok in normal mode ( default mode). Now, i want to change AD9625 to DDC mode(quick config value is 0x82) and get raw I/Q data after "axi_ad9625_core".

I change setting for AD9625 ( as datasheet) via SPI. I change JESD204B core from 8 lane to 2 lane. The data out is still error ( i don't know data arrange before "axi_ad9625_core" and after this)

Below is data out from ILA scope:

It only 2 bus ( one bus is 2 bytes) may be correction data.

Can some one suggest me how to configure reference design to get DDC data.

Thanks you

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  • 0
    •  Analog Employees 
    on May 13, 2019 6:40 AM over 1 year ago

    Hi,

    Did you change anything in the FPGA design? You must reconfigure the whole JESD interface stack, if you want to switch from 8 lanes to 2.

    See this wiki for more info: https://wiki.analog.com/resources/fpga/docs/hdl/generic_jesd_bds

    Thanks,

    -Istvan

  • Dear Istvan,

    This is my Vivado design:

    Axi_ad9625_xcvr:

    util_fmcadc2_xcvr:

    ADI_JESD204_RECEIVE :

    I cannot change axi_ad9625_core, because it fixed every parameter ?

    And this AD9625 settings:

    ad9625_spi_write(dev, 0x05E, 0x82);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x063, 0x8); // single DDC , high bw
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x06E, 0x81); // scrambler - 2 Lane
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x06F, 0x3); //M = 1, S = 4, N' = 16, L = 2, F = 4
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x070, 0x07);//K=8
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    // ad9625_spi_write(dev, 0x072, 0x0F);
    // ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x073, 0x2F);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x131, 102); // NCO = 250
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x132, 0x00);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x0130, 0x03);//ddc gain
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x080, 0xfc);//lane
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ADI_JESD204_Receive settings:

    ad9625_jesd.scramble_enable = 1;
    ad9625_jesd.octets_per_frame = 4;
    ad9625_jesd.frames_per_multiframe = 8;
    ad9625_jesd.subclass_mode = 1;
    ad9625_jesd.sysref_type = INTERN;
    ad9625_jesd.sysref_gpio_pin = GPIO_JESD204_SYSREF;

    I expected that data output order at ADI_JESD204_Receive: I0[N], Q0[N], I0[N+1], Q0[N+1] (LSB to MSB).

    Please help me know data output order at ADI_JESD204_RECEIVE block.

    Thanks you

Reply
  • Dear Istvan,

    This is my Vivado design:

    Axi_ad9625_xcvr:

    util_fmcadc2_xcvr:

    ADI_JESD204_RECEIVE :

    I cannot change axi_ad9625_core, because it fixed every parameter ?

    And this AD9625 settings:

    ad9625_spi_write(dev, 0x05E, 0x82);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x063, 0x8); // single DDC , high bw
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x06E, 0x81); // scrambler - 2 Lane
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x06F, 0x3); //M = 1, S = 4, N' = 16, L = 2, F = 4
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x070, 0x07);//K=8
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    // ad9625_spi_write(dev, 0x072, 0x0F);
    // ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x073, 0x2F);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x131, 102); // NCO = 250
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x132, 0x00);
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x0130, 0x03);//ddc gain
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ad9625_spi_write(dev, 0x080, 0xfc);//lane
    ad9625_spi_write(dev, AD9625_REG_TRANSFER, 0x01);

    ADI_JESD204_Receive settings:

    ad9625_jesd.scramble_enable = 1;
    ad9625_jesd.octets_per_frame = 4;
    ad9625_jesd.frames_per_multiframe = 8;
    ad9625_jesd.subclass_mode = 1;
    ad9625_jesd.sysref_type = INTERN;
    ad9625_jesd.sysref_gpio_pin = GPIO_JESD204_SYSREF;

    I expected that data output order at ADI_JESD204_Receive: I0[N], Q0[N], I0[N+1], Q0[N+1] (LSB to MSB).

    Please help me know data output order at ADI_JESD204_RECEIVE block.

    Thanks you

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