Hi, I am having trouble running my bare-metal application recently because I keep getting this error Rx MMCM-PLL Not locked. What is strange is that before this would only happen every so often at random times when I try to run my application so sometimes it works, and sometimes it doesn't and gets this error. Now, I am getting this error consistently. I thought it was because I changed things in hdl, but I still get this error even when I went back to an older version of my project (which was previously working and had the base hdl provided by analog device's github). I am feeding a ref clock to it as well at 30.72MHz. Does anyone know what may be wrong?
Do you use the talise_config profile posted on our GitHub?
I'm using the talise_config file that you provided me a few weeks ago. I actually have an update on the situation and its that it works again. Do you know what not all causes this MMCM PLL not locked error?
Most likely, the clkgen locking issue is caused by the reference clock. Someone from here can confirm if this clock comes directly from AD9528 or not.
Okay thank you.
Can you describe your architecture ? What changes did you make to the HDL ?
I didn't change much. Just created a custom AXI slave that has two 1 bit output ports called tx1 and rx1. The module is enabled from the PS and after it's enabled, it begins to alternate between setting tx1 and rx1 to 1 every second. (1 second tx1=1 rx1=0, next second tx1=0 and rx1=1) then it repeats. The output of this module is hooked up to the two output ports you see above in my snippet. Tx1 and rx1. And that's it.
If the clock that comes as a reference clock to the transceivers is set at 122.88 MHz and not at 245.76 MHz and the clock generator is not reconfigured accordingly, the VCO of the MMCM PLL is at 4*122.88=491.52 MHz, which is outside of the 800-1600MHz allowed range.
Can you check if it's the case ?