AXI_AD9361 question about R1_MODE


What happens to dac_r1_mode (or adc_r1_mode) when 2 channels of Tx (or Rx) are disabled?
From AXI_AD9361 wiki, it says "if set, core is functioning in single channel mode". Is this the same as REG_CTRL_2[5] for DAC (or  REG_CTRL[2] for ADC)?

The reason for the question is this: In FMCOMMS2 HDL (2018_R1), these signals are ANDed to determine the value of clock divider. For 1R1T, (adc_r1_mode && dac_r1_mode)=1, so divider=2. If one or both directions use 2 channels (e.g. 2R2T), (adc_r1_mode && dac_r1_mode)=0, so divider=4.
If I'll only be using 1RX (adc_r1_mode=1), with 2 channels of TX disabled (dac_r1_mode=??) to save on power, what is my clock divider? I want to do some pre-processing on the enabled channel and need to know what clock I'll be working with.


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