What happens to dac_r1_mode (or adc_r1_mode) when 2 channels of Tx (or Rx) are disabled?From AXI_AD9361 wiki, it says "if set, core is functioning in single channel mode". Is this the same as REG_CTRL_2 for DAC (or REG_CTRL for ADC)?The reason for the question is this: In FMCOMMS2 HDL (2018_R1), these signals are ANDed to determine the value of clock divider. For 1R1T, (adc_r1_mode && dac_r1_mode)=1, so divider=2. If one or both directions use 2 channels (e.g. 2R2T), (adc_r1_mode && dac_r1_mode)=0, so divider=4.If I'll only be using 1RX (adc_r1_mode=1), with 2 channels of TX disabled (dac_r1_mode=??) to save on power, what is my clock divider? I want to do some pre-processing on the enabled channel and need to know what clock I'll be working with.
Even in that case, your clock divider should be 2. Did you try it and does not work?
It does work actually, with the default hdl, drivers and libiio.
But now I want to modify HDL and would like to understand the signals I'm working with.
In the sample application given, does this mean that dac_r1_mode=1 when the TX channels are disabled? I'm not questioning the value, I'm just trying to tie it with the definition given in the wiki.
Hi,Nothing changes on the clock side if the channel is disabled or not. If you are looking for power optimization you can find more questions/threads on EZ regarding this.Andrei
Understood. Was confused with the definition of *_r1_mode signal, saying it means single channel mode. I was sort of looking for a 1R0T, hence the confusion.
So if I set my mode to 2R2T but disable both transmit, *_r1_mode is 0, so divider is 4.
If I set my mode to 1R1T but disable transmit, *_r1_mode is 1 and divider is 2.