Hi,
I'm using a ZCU102 +ADRV9009 combination, using the reference hdl design and no-os SDK setup. I'm trying to setup a design that does receives the RX signal all the signal processing on the FPGA PL fabric and sends it back into the TX chain to transmit out.
from what i understand so far
- the clock on the rx is 122.88MHz, which is double the one on the tx which is running on 61.44MHz
- but the data rate of the ADC and DACs on the adrv9009 is at 122.88MHz at 16 bit resolution
- hence, the data on the tx is 2 samples of 32 bits per channel per clock cycle (2 samples*2 channels*2IQ*16bits=128 bits)
- whereas, data on the rx is 1 sample of 32 bits per channel per clock cycle (1 samples*2 channels*2IQ*16bits=64 bits)
please correct me if there is any mistakes in my assumptions so far.
I have pulled out the RX signal from the axi_adrv9009_core module in the block design and have managed to observe the signal in the FPGA. I am experimenting on how to reinject this signal back into the TX chain within the FPGA, but to no avail. I'll probably need information on the following:
- the bit-level arrangement/format of the tx input
- how the IQ data fits into the 128 bits per clock cycle, if there is an IQ stream of data
- the location where i can inject a RF signal into the TX chain
- how do we pack the Tx samples appropriately (i.e. how does the tx on the adrv9009 read the 2 samples in the frame & in which order?)
Thanks in advance