ADRV9364 HDL optimization


I'm trying to optimize the ADRV9364 HDL to free up some FPGA space for something else. I have the hdl-2018_r1 release.

I'm looking at the HDL design for Pluto as reference, and also checking if I can combine the best of both worlds.

Looking at their data paths:

For ADRV9364:

TX path:  DAC DMA -> UTIL Upack -> DAC FIFO -> AD9361 core

RX path: ADC DMA <- UTIL Cpack <- ADC FIFO <- AD9361 core

For Pluto:

TX path:  DAC DMA -> UTIL Interpolator -> AD9361 core

RX path: ADC DMA <- UTIL Decimator <- AD9361 core

As I'll only be using 1 TX and 1 RX, my questions are:

- Are Upack and Cpack necessary for ADRV9364? Is there value to using these utils for single channel operation, or can I remove these?

- Can the datapath for Pluto be used for ADRV9364 (i.e. use the FIR interpolator and decimator instead of upack and cpack)?  I understand the FIR filters were inserted for low frequency signals, but do they also work for high frequency signals?

- If the Pluto datapath is used, do I still need the DAC/ADC FIFO? If the FIFO are retained, can these be reduced to 2 16-bit channels each (I and Q for one channel), instead of the default 4 16-bit channels?  (And may I also ask why Pluto apparently doesn't need the FIFO?)

- What should the optimal datapath look like? One that allows 1T1R transceiver operation at its full range and with the minimal FPGA utilization.

The only reference I've found where all these IP cores came into play is for FMCOMMS2.

Thanks for the clarification.