I'm trying to optimize the ADRV9364 HDL to free up some FPGA space for something else. I have the hdl-2018_r1 release.
I'm looking at the HDL design for Pluto as reference, and also checking if I can combine the best of both worlds.
Looking at their data paths:
TX path: DAC DMA -> UTIL Upack -> DAC FIFO -> AD9361 core
RX path: ADC DMA <- UTIL Cpack <- ADC FIFO <- AD9361 core
TX path: DAC DMA -> UTIL Interpolator -> AD9361 core
RX path: ADC DMA <- UTIL Decimator <- AD9361 core
As I'll only be using 1 TX and 1 RX, my questions are:
- Are Upack and Cpack necessary for ADRV9364? Is there value to using these utils for single channel operation, or can I remove these?
- Can the datapath for Pluto be used for ADRV9364 (i.e. use the FIR interpolator and decimator instead of upack and cpack)? I understand the FIR filters were inserted for low frequency signals, but do they also work for high frequency signals?
- If the Pluto datapath is used, do I still need the DAC/ADC FIFO? If the FIFO are retained, can these be reduced to 2 16-bit channels each (I and Q for one channel), instead of the default 4 16-bit channels? (And may I also ask why Pluto apparently doesn't need the FIFO?)
- What should the optimal datapath look like? One that allows 1T1R transceiver operation at its full range and with the minimal FPGA utilization.
The only reference I've found where all these IP cores came into play is for FMCOMMS2.
Thanks for the clarification.
Hi,You can remove both packs (upack,cpack). You can also remove the fifo (adc_fifo,dac_fifo), but you will have to run the data path at a double clock, since there is no fifo for clock crossing.
The above cores are required when there is more than one RF channel per direction, in the system.fmcomms4(1 RF channel per direction) reference design is based on the fmcomm2(2 RF channels per direction) reference design. https://wiki.analog.com/resources/fpga/docs/util_cpack
In the case of 2 RF channels (4 data channel) the fifo is used for clock crossing and data sync, since 2 l_clk cycles are required to capture 1 sample for each channel; one I/Q sample per clock period.Do you want to do any processing in the data path(ADC->DMA; DMA->DAC)? modulation... If so, then that will give you your constraints for the optimal data path. Andrei
Noted on the cpack and upack, since we'll only be using one TX and one RX. I think we'll be keeping the FIFO, hence it would look like below:
TX path: DAC DMA -> DAC FIFO -> AD9361 core
RX path: ADC DMA <- ADC FIFO <- AD9361 core
Just one last clarification. We can do the following, right? Or perhaps do some processing/filtering other than interpolation/decimation. I'm assuming that's the correct place to put in the filters, i.e. between DMA and FIFO?
TX path: DAC DMA -> UTIL Interpolator -> DAC FIFO -> AD9361 core
RX path: ADC DMA <- UTIL Decimator <- ADC FIFO <- AD9361 core
Also, your remarks about clocking got me thinking.
The 2x datapath clock assumes an LVDS interface. Is this assumption correct? Because Pluto which uses CMOS interface uses single clock for the DMA and AD9361 core, which is probably 61.44MHz, while ADRV9364 uses a clock divider.
Hi,Right, we recommend doing the processing between the DMA and the FIFO. The fmcomms2 fir filter design was meant as an example of where and how to connect custom logic starting from the reference design. The LVDS interface 6 Rx and 6 Tx lines, runs at DDR (dual data rate), the CMOS, 12 lines per direction, runs at single data rate. Hence, the need for a higher clock.https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/xilinx
Also for optimization check out this https://ez.analog.com/fpga/f/q-a/108562/how-do-i-reduce-power-consumption-of-adrv9364-z7020Andrei
Thanks for the inputs, Andrei.
I have my work cut out for me, but now I have a pretty good starting point.