Unable to Modify DAC Core Frequency ( KCU105 + FMCDAQ2 + Loopback ) using Vivado 18.2

Hi 

Environment Used

Vivado 18.2  = compiled HDL and NoOS from GitHub:

Following is the Log DAC Core Frequency is always showing 61MHz  only.

=====================================================

         Available sampling rates:
        1 - ADC 1000 MSPS; DAC 1000 MSPS
        2 - ADC  500 MSPS; DAC 1000 MSPS
        3 - ADC  500 MSPS; DAC  500 MSPS
        4 - ADC  600 MSPS; DAC  600 MSPS
        5 - ADC 1000 MSPS; DAC 2000 MSPS (2x interpolation)
choose an option [default 1]:
3 - ADC  500 MSPS; DAC  500 MSPS
CPLL ENABLE
CPLL ENABLE
Tx link is enabled
Measured Link Clock: 125 MHz
Link status: CGS
SYSREF captured: Yes
Rx link is enabled
Measured Link Clock: 125 MHz
Link status: CGS
SYSREF captured:                    Yes
 adc_setup adc core initialized (500 MHz).
dac_setup dac core initialized (61065 MHz).
ad9144_datapath_prbs_test : PRBS I channel ERRORS (ab)!.
ad9144_datapath_prbs_test : PRBS Q channel ERRORS (45)!.
ad9144_datapath_prbs_test : PRBS I channel ERRORS (ab)!.
ad9144_datapath_prbs_test : PRBS Q channel ERRORS (45)!.
main ad9680 - PN9 sequence mismatch!
main ad9680 - PN23 sequence mismatch!
daq2: setup and configuration is done
daq2: RX capture done.

===============================================

dac_setup dac core initialized (61065 MHz). should be actually 500MHz 

Unable to do basic loopback test. Kindly looking forward to fix this at the earliest.

Wth Regards,

C P U