Vivado 18.2 = compiled HDL and NoOS from GitHub:
Following is the Log DAC Core Frequency is always showing 61MHz only.
dac_setup dac core initialized (61065 MHz). should be actually 500MHz
Unable to do basic loopback test. Kindly looking forward to fix this at the earliest.
C P U
Moved to FPGA Reference designs community.
Can you tell us which branch (hdl/no-OS) did you use?
Thanks for the reply. I am using the master branch for both. Let me know which branch to be used I will test the same and revert back. I have vivado 18.2 version.
I used no-OS 2018_R1 also check the log it remains same.
Kindly let me know which branch to be used for making external loop back work.