hw/sw co-design interface model


I built a simple block to synthesize it using hdl coder, which is shown in the first figure.  I did it using matlab 2018b ,vivado 2017.4 and BSP of ZC702 with FMCOMMS2/3 you provided in github. But when I proceed in workflow advisor with no errors, my interface model is as shown in the second figure. I do not understand why I see this block  with all of its input and output ports in the interface model. Eventually, Rx_sig_I, Rx_sig_Q, Tx_sig_I,Tx_sig_Q are all related to sending and receiving data between fpga(ZC702) and FMCOMMS3.I included my interfacing in the workflow as third figure. In  this  example, these input-output ports do not seem to appear, but ad9361 transmitter and receiver blocks appear. By the way, when I give the signal from arm to FPGA, after processes in the FPGA, data needs to go to FMCOMMS to be transmitted. Does that happen directly between fpga-fmcomms or arm-fmcomms. In the same example, there is a more complex structure I cannot fully understand. Finally, what should I connect to these ports I mentioned? For example, should I use AD936x blocks from simulink library in the interface model?

Thanks in advance,