I am implementing a version running on ZCU102 that has following setup:
The below picture is the setup:
Running this, I got an error as following log:
[ 6.934332] adrv9009 spi2.1: adrv9009_probe : enter
[ 6.941522] adrv9009 spi2.1: adrv9009_setup:1092: orx_adc_stitching_enabled:1
[ 6.957618] axi_adxcvr 84a60000.axi-adxcvr-rx: cpll: fb_div_N1=5
[ 6.957618] cpll: fb_div_N2=2
[ 6.957618] cpll: refclk_div=1
[ 6.969557] adrv9009 spi2.1: ADIHAL_resetHw at index
[ 7.101318] ata1: SATA link down (SStatus 0 SControl 330)
[ 7.106671] ata2: SATA link down (SStatus 0 SControl 330)
[ 7.507382] adrv9009 spi2.1: adrv9009_do_setup:668 Unexpected MCS sync status (0x0)
[ 7.514972] adrv9009 spi2.1: adrv9009_setup:1092: orx_adc_stitching_enabled:1
[ 7.522083] adrv9009 spi2.1: ADIHAL_resetHw at index
[ 8.059391] adrv9009 spi2.1: adrv9009_do_setup:668 Unexpected MCS sync status (0x0)
[ 8.066992] adrv9009: probe of spi2.1 failed with error -14
[ 8.073101] PLL: enable
[ 8.075664] PLL: shutdown
Could you help me to identify the root cause?
PS: I've successfully run ADRV9009 eval board on HPC0 with clock and sysref generated by AD9528 on the same.
Thanks and Regards,
To elaborate the problem, let's me summarize the process of MCS as in the driver's note:
After the verification step, the status I got was 0x00. That means no synchronization in JESD SYSREF, Digital clock, CLKPLL, CLK DIVIVER.
I wonder what is the root cause of the issue. I have several questions:
In that case, sysref_req gpio should be assigned to the equivalent pin in FMC-HPC1 rather than FMC-HPC0.
2. I wonder does it send 3 SYSREF pulses successfully?
3. Could RESET_B (ad9528_reset_b) cause this issue?
What version of linux/HDL are you using ? We've recently updated the firmware for ADRV 9009 in our linux repository.
2. Can you use an ILA to monitor the SYSREF on the FPGA, to see if the sysref is generated as expected ?
3. If reset_b is 0 on either of the AD9528, and you're using both in your design, it will cause an issue.
thanks for your reply.
We updated the most recent firmware for ADRV9009. I used HDL branch 2018_r1 for this implementation.
For my first question: "Regarding generate SYSREF pulse, instead of sending sysref_req to the slave AD9528 (on HPC0), FPGA have to send it to the master AD9528 (on board plugged in HPC1)". Do you have any comment?
In addition, do you think to any other clues which can cause the MCS issue?
I've checked signals with ILA when MCS was called:
So, the root cause is not above signals.
I have seen this issue when I change Pattern mode (in register 0x0403) from the AD9528. Default setting is continuous (bits [5:4] = 01), I have got this error when I change it to N-shot (bits [5:4] = 00)