How to enable cyclic transmission using DAC_DMA on ad9361?


I am attempting to achieve BPSK output from my FMCOMMS3+zedboard No-os set up. I am trying to achieve this using a ROM IP core I built using verilog. (picture of IP design below)

My IP core is simple, outputs value of Q_out=16'b0000000000000000; and I value of  16'b0111111111110000; OR 16'b1000000000010000; depending on the bit I want to transmit (0 or 1). I am clocking the subsystem using the out put of the Util_clk_div which should be running at 122.88Mhz  as I am operating in 1Rx1Tx mode (thus the out put of the clk divider is DAC_CLK / 2). In the SDK    I include #define XILINX_PLATFORM      in  Main.C    and un-comment  #define DAC_DMA_EXAMPLE     in Config.h . 


My carrier frequency is 150Mhz, this is so that I can observe the bit flip of my BPSK RF out on my oscilloscope. 

My issues:

1) When running the program in SDK I observe a modulated waveform for an instant and then just a Sine wave at 150Mhz which is most likely just my carrier freq. Do I need to enable a cyclic flag somewhere for continuous transmission from DMA?

2) The modulated wave form I see for that brief instant is Amplitude modulated and not PSK. Is my method of modulation (described above ie shifting IQ values) not correct ? Or is it just that my carrier frequency is too low? 

Could the DAC enable/Valid connections be the issue?