I am attempting to achieve BPSK output from my FMCOMMS3+zedboard No-os set up. I am trying to achieve this using a ROM IP core I built using verilog. (picture of IP design below)
My IP core is simple, outputs value of Q_out=16'b0000000000000000; and I value of 16'b0111111111110000; OR 16'b1000000000010000; depending on the bit I want to transmit (0 or 1). I am clocking the subsystem using the out put of the Util_clk_div which should be running at 122.88Mhz as I am operating in 1Rx1Tx mode (thus the out put of the clk divider is DAC_CLK / 2). In the SDK I include #define XILINX_PLATFORM in Main.C and un-comment #define DAC_DMA_EXAMPLE in Config.h .
My carrier frequency is 150Mhz, this is so that I can observe the bit flip of my BPSK RF out on my oscilloscope.
1) When running the program in SDK I observe a modulated waveform for an instant and then just a Sine wave at 150Mhz which is most likely just my carrier freq. Do I need to enable a cyclic flag somewhere for continuous transmission from DMA?
2) The modulated wave form I see for that brief instant is Amplitude modulated and not PSK. Is my method of modulation (described above ie shifting IQ values) not correct ? Or is it just that my carrier frequency is too low?
Could the DAC enable/Valid connections be the issue?
Try out the following:
1) Define two input signal for your IP (req_I and req_Q). Use this inputs to validate the data on I_out and Q_out. Meaning when req_I is high, you will drive the next data to the I_out, and you do the same for Q.
2) Connect this modified core directly to the axi_ad9361 core's dac_data_i0 and dac_data_q0 port, and connect the dac_valid_i0 and dac_valid_q0 to your req_I and req_Q.
Let me know the result. Because you're bypassing the DMA completely, you don't really care about its configuration. Just make sure that the DAC_DDS_SEL register of the axi_ad9361 is set to 0x2. (input is DMA)
Thanks for the reply!
So I have done what you suggested and will attach a picture of my IP diagram to this post.
The resulting wave form out of TX A sma of my daughter board (fmcomms3-ebz) is an Amplitude modulated signal of the carrier frequency. This is not expected, as the IQ values I am switching between should be supplying a BPSK modulation to the carrier. Note that the carrier frequencies I am using are sufficiently low, so that I can view them on my Oscilloscope (tested using 150Mhz carrier and 300 Mhz carrier --> gave same result). I will attach a picture of my oscilloscope output to this message as well.
Is my method of switching between the IQ samples incorrect ? It seems to me that the amplitude of the resulting RF after the IQ mixer is not being conserved, which is strange. Or is my carrier frequency too low to observe BPSK (I have no clue as to why this would be the case, maybe the clock for my IP modulator is too high and should be divided).
**note, I know that 300Mhz is pushing it for my scope, but it still satisfies Nyquist so I believe that the information the scope is presenting is true. ie that even at a carrier frequency of 300Mhz I observe AM not BPSK modulation**
I don't think that your scope has enough bandwidth for measuring a 150 or 300 MHz signal. A good rule of thumb is to have three times higher bandwidth than the maximum signal frequency of your analog signal on an oscilloscope with a flat frequency response. (according to keysight) After checking your scope's datasheet you have 200MHz max, which is not enough in this case.
You should drive your modulation IP with axi_ad9361_l_clk, it seems to me, you don't have any clock connected to it. You may want to verify your modulator in simulation first, to make sure that it functioning correctly.
Thanks, I will try to get my hands on a spectrum analyzer/higher bandwidth scope. (I always thought two times bandwidth was fine , yikes!)
For my modulation IP, I am driving it using the output of the "util_clkdiv" IP, which divides the axi_ad9361_I_clk, do you suggest I run it with the "full" clock rather than the divided clock?
Again, thank you for the reply and assistance!
Yes, you have to use the axi_ad9361/l_clk.