The AD9371 Zynq evaluation code loaded from the SD card seems to be much more mature and fully functioning than the hdl_2018_r1 FPGA code and No-OS software available in the repository. For example, the No-OS/hdl_2018_r1 configuration seems to require a 2R2T configuration while the Zynq evaluation image seems to support a 1R1T configuration (using the Transceiver Evaluation Software for configuration).
1. Does the AD9371 Zynq evaluation platform use a different code base (HDL and API) than the No-OS/hdl_2018_r1 repository?
2. If so, is that code base available? for FPGA code? for API code? for TES application?
3. Does Analog Devices plan to modify the No-OS/hdl code to support the configuration options available in TES?
We're specifically interested in
1. moving to a 1R1T configuration with reduced JESD lane rates (using 4 JESD lanes)
2. supporting a 1R1T configuration over 2 JESD lanes
I have also moved this question to FPGA Reference Designs section for additional comments.
1. Yes, it's a different design.
2. The sources are not available.
3. These changes can be made, but I will let someone from here to explain how. For making things easier, using a newer branch than hdl_2018_r1 might be required.
Thanks. I just wanted to make sure we're starting from the right code base.