I am working with the FMCOMMS 2 reference design running the fmcomms 3-ebz +zedboard combo.
I wrote a simple BPSK modulator in verilog that is clocked using the "Clocking Wizard" in Vivado. The output of my BPSK modulator is simply "0000 0111 1111 1111" or "0000 1000 0000 0001" depending on the bit (0= no phase shift, 1 is phase shift of pi). I connected the output of my modulator to the input of the "DAC FIFO core" and left the valid signals alone, while disconnecting the output of the "DAC UPACK core". The clock running the modulator (generated by the clocking wizard in Vivado) should regulate the data rate for the flipped bits (obviously will be less than the sys_clock), I am running the modulator at 10Mhz currently. My question is: what mode should I put the TX line in using the XSDK to see the modulated output? Will all modes show this ? For example if I run Console commands does the data for transmission come from my HDL core?
My confusion stems from the picture attached to this post. It seems that I need to choose DMA on the Mux to actually transmit my IQ samples using my current set-up.
As always any help is appreciated !!!
I will attach a picture of the IP integrator design below for reference.
Yes, you are right, you should choose the DMA path in software.
Regarding your design, you will have problems if you'll run the modulator with an asynchronous clock to the dac_clk. You have to drive your modulator with the dac_clk, instead of the 10MHz. The main reason is that the device (AD9361) control's the data rate of the data path inside the FPGA. So whatever processing do you trying to do in the TX path, you have to run your logic at the dac_clk rate, using the dac_clk source.
Thanks for the reply! So if I am trying to output a data rate of 10Mhz, is it recommended to alter the DAC 's frequency in software to achieve this?
Also the DAC clock comes from the AD9361 (I believe the frequency can be changed in software) where is this clock source in the reference design? Is it the output of the "util_ad9361_divclk" block (picture below) or is it the "rx_clk" connected to the "rx_clk_in_p" port (image of constraint below)?
Thanks again Csoml!