How to exchange reg in Different Clock Domain


   I want to design my own IP like axi_ad9361 with some register can be changed by PS. So I code as the axi_ad9361 structure.

axi_module -> up_axi-> 

                    ->my_module -> up_my_module


But Design Runs reported too high WNS and TNS.

WHS -7.634ns, THS -1921.247ns

I want to know how to handle this problem, and which code style is best to synthesis?

Can you give me some information about this problem? books or docs...



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[edited by: caojiahui at 8:33 AM (GMT 0) on 21 Jan 2019]