I want to design my own IP like axi_ad9361 with some register can be changed by PS. So I code as the axi_ad9361 structure.
axi_module -> up_axi->
->my_module -> up_my_module
But Design Runs reported too high WNS and TNS.
WHS -7.634ns, THS -1921.247ns
I want to know how to handle this problem, and which code style is best to synthesis?
Can you give me some information about this problem? books or docs...
I read implementation reports, Inter-Clock Paths have highest Slack, most is from up_rdata_int to my blk_mem_gen ip.
I have some signals from up_axi_module to control a blk_mem_gen ip.
Hi,Take a look at https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_adc_common.v#L411-L441
I also have a question.
I want to use axi_lite to read a block mem, I don't want to add a axi_bram_ctrl, How to add this in my ip.
Because use up_xfer_cntrl have delays, write addr and read data will not sync
We use up_xfer_cntrl for clock domain crossing, the PS and IPs.Your question is more suited for Xilinx forums, it is outside our scope.We don't have any documentation or examples that could help you with this.Andrei