Can somebody provide me some information about hard_tuning timing of digital interface between AD9361 and FPGA?

I had download some example about AD9361 and FPGA, but  soft_tuning is used to timing between us. I want to use hard_tuning, and in the project ,there is information about hard_tuning, but some signal is connected to edk core, I can't understand how the signal generate. And I want to use these part HDL code, who can help me?

expect reply!