I am working with Zedboard+FMcomms3 setup and operating off the up to date HDL running the NO-OS driver. I am fairly comfortable using the driver at this point, and I am now attempting to modulate the carrier with custom data. I would like to implement BPSK in my design and was wondering if there are any DSP libraries that AD recommends to achieve this with my specific set-up. Or perhaps there is an easier method for modulation that is inherent to the driver that I haven't stumbled upon yet (this would mean that I'm not actually comfortable with the driver I guess). Worst case scenario would be me writing the modules in C from scratch.
Goal is to implement BPSK on a 2.4Ghz carrier according to a pre-defined Look Up Table in my real time system.
Any help is appreciated! Thanks !
It is generally recommended to not do any DSP on the ARM itself, that is what the FPGA fabric is for. For creating IP cores on the FPGA we recommend using: HDL Coder from MathWorks, System Generator For…
You'll want to place IP between the Pack and FIFO cores. See this example here:https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt
If you don't want to add DSP to a channel just leave…
DDSs use a cordic implementation in the axi_ad9361 interface core.
It is generally recommended to not do any DSP on the ARM itself, that is what the FPGA fabric is for. For creating IP cores on the FPGA we recommend using: HDL Coder from MathWorks, System Generator For DSP from Xilinx, Vivado HLS, or other tools within Vivado.
Thanks for the reply. So it looks like I am going to make an IP core that will take care of the BPSK. My question now is about the placement of the core. Should the modulation core be placed before DAC_FIFO in the IP block design?
What does din1-4 correspond to ? My assumption is that din1=I1 and din2=Q1, din3=I2, din4 =Q2. By virtue of the device I am using (Fmcomms-3) my din3&4 would not be doing anything (1tx1rx mode) so is it fine to leave these connections alone?
If you don't want to add DSP to a channel just leave it connected as is.
My IP module requires a carrier with 180 degree phase shift. Is the carrier generated from DDS of a Look up table ? and if so does this occur in the AD9361 core?
I'll attach the image i am referencing to this message.
Thanks again for the replies.
Can you verify that my current interpretation of the system is correct.
1)The 16bit I and 16bit Q samples fed into the DAC core have nothing to do with the carrier generation.
2) The carrier frequency is generated by the TX and RX synthesizer on the physical AD9361 IC.
If both of those are correct. My final question would be
How do I obtain a phase shift in my carrier?
As my IP core requires the original carrier and a 180 degree shifted carrier.
The DAC is actually 12 bits. See doc about the 16/12 bit interfaces: https://wiki.analog.com/resources/fpga/docs/axi_ad9361#internal_interface_description
The IQ mixer in the chip creates the carrier. If you need addition phase shift just rotate your input data on one of the channels.
There's one thing I didn't understand from the answer. What is meant by rotate the input data? Do you mean taking the one's complement? Do you mean a bit-wise shift and rotate for each element in the input data? Or is it something else? I'd really appreciate if you provide a simple example.