I am using Vivado 2017.1
HDL project adrv9361z7035/
no-OS with adc_capture enabled
1- I can successfully capture an input sinusoidal
2- I added a Nyquist FIR in multiple channel config between the util_wfifo_v1_0 and util_cpack_v1_0
concat Fifo outputs (I0,Q0,I1,Q1) => FIR tdata(63:0)
used din_valid_1 => FIR tvalid
set FIR Clock frequency = 4 x input sample frequency
I_clk => FIR aclk
and passed the FIR output and m_axis_data_tvalid to the dma
Everything worked fine
3- I need to implement a high order correlator (FIR) so I wanted to try running the FIR aclk at 100 MHz (FCLK_CLK0) ==> DID NOT WORK
4- I passed the din_valid_1 through an Edge detected clocked with the 100 MHz to provide the FIR tvalid with a one cycle valid signal ==> DID NOT WORK
Any idea why?
PS: I looked at the example "https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt" but it uses aclk = 4 times the Fs
Forgot to mention that I changed the no-OS such that
rx_samp_freq (Fs) = 532800 Hz (0.5328 MHz)
I_clk = 2.1312 MHz (4xFs)
Hi,I have not checked what is the minimum sampling rate. You said that you had some processing done in the data path, and it worked. At this sampling rate? Sampling frequency seams pretty low to me. I know on Pluto there are the interpolation and decimation modules because there are some problems at lower sampling rates.
The valid data on the util_rfifo comes only once in every 4 l_clk cycles (2.1312 MHz).Is this data throughput enough for your filter?On what clock are you reading data from the fifo? 100MHz?Andrei
I DO have the console uncommented for all tests
Changing the clock and the valid duration didn't fix the problem...
I can send you the full project OR if you take the original design from GitHub and an FIR (single rate...no decimation) between the FIFO and adc_pack to filter the 4 lines (I0, Q0, I1, Q1) you can see the problem...when FIR (aclk) runs at I_clk, everything works fine....if you run the FIR (aclk) at 100 MHz, doesn't work
HI,I will take a closer look and come back to you tomorrow with an answer.Andrei
Thank you Andrei
Hi,I told you to set the reading clock of the util_wfifo(adc_fifo) to 100MHz. This will not work; util_wfifo is used for clock domain crossing but only at fixed ratios to downscale the clock domain (1:1/1:2/1:4/1:8). I apologize for that, forgot about it. We only have the util_rfifo documented which uses the same principle in a reverse manner.You have to replace util_wfifo with util_axis_fifo which doesn't have this constraint; unfortunately, we don't have any documentation for it at this point. You can find examples on how to use it in other IPs as the axi_dmac; or use a Xilinx FIFO.Andrei
Hello Andrei and thank you very much for your help.
I successfully added the FIR but this time I added it between the CPAC and DMA...all FIFO/CPAC/FIR are running at 100MHz and output of system is GOOD...I may have to revisit this issue if I add a decimation filter in the HDL Rx path later (instead of lowering the ad9361 ADC clock -> quantization noise)