I am using Vivado 2017.1
HDL project adrv9361z7035/
no-OS with adc_capture enabled
1- I can successfully capture an input sinusoidal
2- I added a Nyquist FIR in multiple channel config between the util_wfifo_v1_0 and util_cpack_v1_0
concat Fifo outputs (I0,Q0,I1,Q1) => FIR tdata(63:0)
used din_valid_1 => FIR tvalid
set FIR Clock frequency = 4 x input sample frequency
I_clk => FIR aclk
and passed the FIR output and m_axis_data_tvalid to the dma
Everything worked fine
3- I need to implement a high order correlator (FIR) so I wanted to try running the FIR aclk at 100 MHz (FCLK_CLK0) ==> DID NOT WORK
4- I passed the din_valid_1 through an Edge detected clocked with the 100 MHz to provide the FIR tvalid with a one cycle valid signal ==> DID NOT WORK
Any idea why?
PS: I looked at the example "https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt" but it uses aclk = 4 times the Fs
Forgot to mention that I changed the no-OS such that
rx_samp_freq (Fs) = 532800 Hz (0.5328 MHz)
I_clk = 2.1312 MHz (4xFs)
Hi,I have not checked what is the minimum sampling rate. You said that you had some processing done in the data path, and it worked. At this sampling rate? Sampling frequency seams pretty low to me. I know on Pluto there are the interpolation and decimation modules because there are some problems at lower sampling rates.
The valid data on the util_rfifo comes only once in every 4 l_clk cycles (2.1312 MHz).Is this data throughput enough for your filter?On what clock are you reading data from the fifo? 100MHz?Andrei
Hello Andrei and thanks for your reply.
The minimum sampling rate (Fs) for the picozed is 25MHz/48 = 520.8KHz and that requires enabling the FIR filter inside the ad9361.
I am adding an FIR in the HDL receiver side between the FIFO and the util_cpack and clocking this FIR with I_clk (4Fs). FIR is in multichannel mode with input(0:63)=[I0 Q0 I1 Q1]. This Worked OK
If I run the FIR at a clock = 100 MHz (FCLK_CLK0), the filter DOES NOT Work.
-The valid data on the util_rfifo comes only once in every 4 l_clk cycles (2.1312 MHz).
Correct...and I tried passing it through an edge detector tat runs at 100 MHz to have a valid for only one cycle of the 100 Mhz==> Did NOT work
-Is this data throughput enough for your filter?
Yes...the filter is single rate so out and input are same rate
-On what clock are you reading data from the fifo? 100MHz?
No...I didn't change the fifo or cpack settings
din_clk = I_clk
dout_clk = I_clk/4
The picture below uses the original design with Fs = 30.72 MHz and I_clk = 122.88 MHz...adc_capture works fine and I see the input signal correctly...I noticed that the console doesn't print the menu or anything after:
ad9361_init : AD936x Rev 2 successfully initialized
Hi.If you want more messages from the system configuration part make sure these lines are uncommented.I suggest changing the clock for reading the data from the util_rfifo. This fifo is used for clock domain crossing, as you are interested in processing the data at 100MHz change it accordingly.https://wiki.analog.com/_media/resources/fpga/docs/hdl/fmcomms2_fir_2.svgThe whole path from adc_fifo to DMA can run at 100MHz. You must pay attention to the data throughput through the interfaces (enable and valid signals).Andrei
I DO have the console uncommented for all tests
Changing the clock and the valid duration didn't fix the problem...
I can send you the full project OR if you take the original design from GitHub and an FIR (single rate...no decimation) between the FIFO and adc_pack to filter the 4 lines (I0, Q0, I1, Q1) you can see the problem...when FIR (aclk) runs at I_clk, everything works fine....if you run the FIR (aclk) at 100 MHz, doesn't work