Integrate FIR filter into the ADRV9361 RX HDL design

Hello all,

I am using Vivado 2017.1

HDL project adrv9361z7035/

no-OS with adc_capture enabled

1- I can successfully capture an input sinusoidal

2- I added a Nyquist FIR in multiple channel config between the util_wfifo_v1_0 and util_cpack_v1_0

concat Fifo outputs (I0,Q0,I1,Q1)  => FIR tdata(63:0)

used din_valid_1 => FIR tvalid

set FIR Clock frequency = 4 x input sample frequency

I_clk => FIR aclk

and passed the FIR output and m_axis_data_tvalid to the dma

Everything worked fine

3- I need to implement a high order correlator (FIR) so I wanted to try running the FIR aclk at 100 MHz (FCLK_CLK0) ==> DID NOT WORK

4- I passed the din_valid_1 through an Edge detected clocked with the 100 MHz to provide the FIR tvalid with a one cycle valid signal ==> DID NOT WORK

Any idea why?

PS: I looked at the example "https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt" but it uses aclk = 4 times the Fs

Regards,

Murad