Inserting FFT core for verification of Rx path using HDL AD9361.in linux SW

Hi,

Yes, it is correct. You might want to consider the upac/cpack cores if only one channel is enabled at a time.
https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt

Andrei

Dear Andrei

I integrated Xilinx FFT core in the path (util_ad9361_adc_fifo----->xfft(v.9)) . I am interested in data of dout_data_0 and dout_data_1.

1- For testing purpose I combined ( dout_valid_0 and dout_valid_1 ) and connected  to s_axis_data_tvalid. of the fft core.

2- concatenated dout_data_0[15:0] and dout_data_1[15:0] and connected with s_axis_data_tdata[31:0] , connected

s_axis_tdata_tlast to a counter (that assert FFT_tlast if counter reaches to certain value ). and xfft clock is (aclk ---> din_clk )

3- m_axis_data_tdata[31:0] -----> ILA(probe 31:0) ,

    m_axis_status_tdata[7:0] ----> probe 7:0 ,

   m_axis_status_tvalid---probe ,

   m_axis_data_tlast----->probe ,

   m_axis_data_tuser[23:0] ---> probe ,

   m_axis_data_tvalid ----> probe ,

   event_frame_started--->probe ,

   event_tlast_unexpected ----> probe ,

   event_tlast_missing ----> probe ,

   event_fft_overflow---->probe ,

   event_data_in_channel_halt ----> probe

4- after connecting equipment ( signal generator ----> RX1A) and I got the attached result.

update : I added FFT core for other channel also . I got the following timing error .

snap is attached

Hi,

I will have to take a closer look. Didn't have time today. I will try to have an answer for tomorrow.

Andrei

I resolved WNS and TNS negative vlaues issues. that is resolved . Thanks. 

andrei_g

need your guidance in interpreting the FFT result .  the snap is attached . 

1- For confirmation of FFT core setting , I checked by generating a signal from DDS core and injecting into FFT core and I got the correct index number by using the formula ( index number (on which peak detected ) X Fs/N where Fs is sampling frequency and  N FFT points . so my FFT core setting is correct .

2- Now after inserting FFT core  in Rx data path (util_ad9361_adc_fifo----->xfft(v.9)) . I got the result (snap is attached ) . and applied signal is 135Mhz on RX1A and LO (setting by IIO Oscilloscope Rx LO=136) . and FFT core is running is on 100Mhz clock rate(adc_fifo output rate ). Using the above formula and LO , I tried to calculate the right index for the FFT of applied signal but that doesn't seems correct. (Image attached).

Can u please check this and suggest me if this approach is correct. if not, please guide me to find the correct index   ? .and what would be suggested waveform of tdata?????

ALL the snaps and ILA data is attached for reference.fifo_out.xlsxFFT_output.xlsx

FFT of 1Mhz Signal applied through DDS, checked on ILA. Got correct results.

ADC fifo output before packing of data. 

Data path of the overall design, Reference design is not modified but another core is added like shown in this figure

Hi,

Change your signal to 137MHz (LO + sine). But I don't think you will get a valid result with this approach. You need a proper modulated sine wave.
What type FIFO(adc_fifo) have you connected there, and can you give more details about its connections?

travisfcollins can you comment on this?

Andrei

Based on your configuration your tone should appear at -1MHz. If you are not FFT shifting the output it may appear at FS/2 -1MHz.

-Travis

Dear andrei_g & travisfcollins

Thank you for your valuable suggestion .i performed some task . sent the captured data to MATLAB and checked the frequency on Simulink Spectrum Analyzer. 

Settings were following 

LO=155Mhz 

RF BW=40MHz

Sample Rate=61.44MSPS

ADC FIFO(ADI version 2018_r1) = 100Mhz

Simulink Spectrum analyzer sampling frequency = 100 Mhz

RF IN (RX1A) = maximum Peak 

My understanding from your suggestion that if Lo=155 RFin=156 the peak shall be at 1 , and so (RFin-LO) . but as evident from the above table the difference is increasing by factor more or equal to 1.6 factor . Kindly your views on this .

BR

Hi,

Can you post here the whole interface between axi_ad9361 and adc_fifo?

Andrei