Good morning,I have just received an AD-FMCOMMS4-EBZ FMC Module and I am trying to use the HDL Reference Designs provided by Analog (Reference link: wiki.analog.com/.../reference_hdl)I am using Vivado 2018.1 and I the hdl-2017_r1 archive (because newer does not support anymore the AC701 board).When I launch the make inside the projects/FMCOMMS2/ac701 folder, the process give an Error 139 which consists in an "Abnormal Program Termination (11)" in the log file of the axi_ad9361.I have also tried to launch the single tcl scripts to build the libraries but after some seconds Vivado exits for a crash.Have you got some suggestions to run this demo example?One of the reason I have bought the FCM module is the compatibility with the AC701 board for SDR applications.Otherwise, do you have an already compiled and working project for Vivado only for this specific platform?Thank you in advance for cooperation.Best Regards,Andrea
Hi Andrea,Unfortunately, we don't have the files for ac701 https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/quickstart/microblazeUse Vivado 2016.4 with hdl_2017_r1 https://github.com/analogdevicesinc/hdl/releasesOr use Vivado 2018.2 and bring back the ac701 files from the 2017_r1 release to the hdl_2018_r2.We had problems with customers trying to use Vivado 2018.1 in the past.Andrei
thank you so much for your answer.
For the moment I have tried with Vivado 2016.4 and it works well until the bitstream generation phase, because there is a problem with the "Tri Mode Ethernet MAC" IP Core License.
If I don't buy the License from Xilinx I won't be able to run the example. Am I wrong?
Thank you again for your answer.
Hi Andrea,What software do you want to use? Linux or no-OS(bear-metal)?https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/microblazehttps://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/no-os-setupAndrei
I will go for the no-OS.
Thanks for the link.
I will try with that User Guide.
I am trying to use the no-OS configuration and I have a question.
The steps I have executed are the following:
Since I have not succeeded in using the example (no interaction with UART for configuration), do you think I have followed the right process or have I missed something?
I have encountered a problem in the process, but I don't know if it is relevant.
I have started to use SDK in Vivado 2016.4, as suggested by you. I have run the project and I have obtained in the UART display the following: "ad9361_init: AD936x Rev 2 successfully initalized" and then "Done." No interactions were allowed.
I tried to modify some configuration parameters. But due to some strange behaviours I was not able to operate in the Vivado SDK configuration windows (I think it is a problem between my OS RHEL 7.4 and Vivado 2016.4).
So I moved to Vivado 2018.1 with the already build project and your bitstream. I opened the SDK and import all the src files. I have also build the project but when I run nothing happens.
Have you any idea to help me run the example?
Thank you very very much for cooperation.
Hi,Using a hdf file generated by a different Vivado version than the SDK will not work.
ad9361_init: AD936x Rev 2 successfully initalize
xsdb xilinx_capture.tcl MICROBLAZE 0x80800000 32768 4 16
To get more interaction you have to change the C code.As I said, if you want to use newer Vivado tools use 2018.2, you will encounter problems with 2018.1Remove the Ethernet from the block design and you will not require a license for the time being.Andrei
I have succeeded in using the no-OS example with my boards AC701+FMCOMMS4.
I am able to use the UART to configure the transceiver and obtain RF output signals.
Now I would like to integrate a modulator developed by me inside the design, in order to have in output the modulated signal.
Can you help me in understanding where the I and Q samples have to be provided, which is the sample rate I have to provide and if there are other things to be considered?
I have not found diagrams or detailed documentation about the example project.
Just to inform you, I have also succeeded in removing the Ethernet core from the design in order to be able to re-run synthesis, implementation and bitstream generation.
Thank you in advance for cooperation.
Hi Andrea,Have you seen the fmcomms2 fir filters example?You will have to add your module instead of the filters.There are also a lot of threads on this topic on EngineerZone. Take a look you might find the answer.
We try to keep things clean for other users to find answers here. Since the original question was addressed, and this thread is closed. For the future question, please open a new thread, describing the project, software version and the issue you are facing. Thanks,Andrei
Ok. Sorry for using the same thread.
Thank you for the answer. I have never seen the FIR filters example.
I will study it and try to implement my modulator.
Thank you again.
In case of need I will open a new thread.