Hi, I am doing project on zedboard integrated with AD-FMCOMMS2-EBZ of Analog Devices.
What I am trying to do is basically adding my own IPs within the reference HDL design provided here(https://github.com/analogdevicesinc/hdl).
For simple test, I added BRAM block within the design and tried to access it from PS by using 'mmap'.
However, it resulted in SIGBUS error which means the address of BRAM is not valid.
All the other blocks connected with PS through AXI Interconnect work well. I can access to those blocks without any problems.
But only my custom block cannot be accessed from PS.
(I just added my own block to the design, generated bitstream, and exported to hdf file)
I would really appreciate any advice for my problem.
Thanks ahead of time!
You should double check the connections of the BRAM (look at the implementation log, search for warnings or critical warnings related to your BRAM), check the value of the base address, the BRAM's device tree entry. It should be a simple mistake somewhere.
I double checked base address, so it may be not be the reason.. Only critical warning shown after modifying the design is timing failure. Do you have any idea related with this timing issue?
If you share the log file, I will have.
which log file would help you understand?Many log files in the project directory..
runme.log runme.logThese are implementation and synthesis log files..