Hello,
ADRV9009 supports mode "ORX and RX datapath using the same framer". As I understand, they will use the same physical lanes to transport data to FPGA.
But, in FPGA, one RX_PHY is only mapped to either RX or ORX. So, my question is: "does FPGA reference design of ADI support that mode?"
Thanks in advance,
Trung Nguyen
Hello,
it does not supports that, you need separate physical lanes and framers for each path. Please correct me AdrianC
Thanks,
Laszlo
Hello,
We haven't tested the mode and it currently is not supported by the HDL reference design. We'll investigate and let you know if it's easy to implement.
Regards,
Adrian
We won't be supporting the mode in our reference design in the near future. We put it on our to do list, but will take a while until it's going to be available.
Regards,
Adrian
hi,i use the hdl project demo you provide.
i need to know the data order in the ip axi_adrv9009_core.
adc_os_data_i0[31:0]/adc_os_data_q0[31:0]/adc_os_data_i1[31:0]/adc_os_data_q1[31:0],when the sample rate is 491.52Msps,what is the data order????i want to get the right data from the 4x32bit data?how it comes?what should i do to get the right data??
hi,i use the hdl project demo you provide.
i need to know the data order in the ip axi_adrv9009_core.
adc_os_data_i0[31:0]/adc_os_data_q0[31:0]/adc_os_data_i1[31:0]/adc_os_data_q1[31:0],when the sample rate is 491.52Msps,what is the data order????i want to get the right data from the 4x32bit data?how it comes?what should i do to get the right data??
