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QPLL support in axi_adxcvr and util_adxcvr

I am working with the ADRV9371/ZCU102 reference design and am trying to program the ADRV9371 with a profile for 204.8 MSPS transmit. The AD9371 driver (and supporting drivers) appear to turn this into a request for JESD lane rate of 4.096 GHz. The default device tree and design appear to be set to use QPLL for the transmit lanes. 

The requested lane rate of 4.096 GHz would require a QPLL VCO of 8.192 GHz (twice the lane rate). The Xilinx documentation UG576 lists two VCO bands for the QPLL, with the lower band supporting 8.192 GHz, but the software driver appears to be hardcoded to the upper band only (xilinx_transceiver.c).

Do the axi_adxcvr/util_adxcvr cores support both QPLL bands listed in UG576? 

Related SW issue: ez.analog.com/.../ad9371-unable-to-load-profile-generated-from-filter-wizard-clk_core_disable-and-clk_core_unprepare-warnings

  • Hi,

    Currently the axi_adxcvr/util_adxcvr support just the upper band (QPLL0), it's on our TODO list to add  QPLL1 support asap.

    Thanks,

    -Istvan

  • Thanks for the info, Istvan. Are you in a position to roughly estimate whether this would be days, weeks, months?

    I'm also trying to pursue other options in parallel to enable my desired AD9371 transmit rate -- are you aware of any software driver or reference design limitations associated with switching from the QPLL to CPLL? It looks like the CPLL should support the desired lane rate and I think this switch can be controlled by a device tree setting without any changes to the reference design.

    Regards, 

    -Jeff

  • Hi,

      I received your request for me to continue to ask the same question. Asking support under this thread:https://ez.analog.com/fpga/f/q-a/103549/zc706-adv7511-display-there-are-something-wrong-in-color.I just clicked the button before I could see it clearly, thinking it was to accept your answer. 

    I don't know how to send you a message about my fault, so I'm apologize to you here.

  • Hi Jeff,

    I'm adding to the discussion, he can give you a rough estimate.

    You can switch to CPLL, but be aware that RX/ORX are using CPLL at the moment. What is your targeted lane rates for  TX/RX/ORX ?

    Thanks,

    -Istvan

  • No problem at all @Really. We just trying to keep our forum clean, so everybody can take advantage of it.

    Thanks for your understanding,

    -Istvan

  • Hello,

    I would estimate the soonest would be 1 month until doing improvements to the util/axi_adxcvr IPs, but with the new year, it's likely to be later than that.

    Regards,

    Adrian

  • Thanks, I am currently trying to load a profile with TX/RX/ORX at 204.8/102.4/204.8 MSPS which appears to request a lane rate of 4.096 GHz for all three. Details below were obtained with QPLL still enabled:

    • When the device clock is set to 204.8 MHz, it looks like the driver first requests lane rates of 8.192 GHz for all three TX/RX/ORX. After this fails, the driver follows up with a request for a 4.096 GHz lane rate for all three.
    • When the device clock is set to 102.4 MHz, the driver requests a lane rate of 4.096 GHz for all three.

    Regards,

    -Jeff

  • Hi Adrian, thanks for the estimate. I'm definitely interested to see if this improvement will help my issue, and in the meantime, I'll continue to look for workarounds.

    Regards, 

    -Jeff

  • Hi Jeff,

    I think you can try to use CPLL only, for both transmit and receive. The easiest way to set this up is to reset the QPLL_ENABLE parameter for the TX axi_adxcvr core in the block design. You also should adopt the output clock selectors too (SYS_CLK_SEL, OUT_CLK_SEL).

    Thanks,

    -Istvan

  • Hi Istvan, thanks for the tips. I've modified the HDL Reference Design as follows (match the QPLL_ENABLE, SYS_CLK_SEL, and OUT_CLK_SEL parameters of the axi_ad9371_rx_xcvr and axi_ad9371_rx_os_xcvr blocks):

    startgroup
    set_property -dict [list CONFIG.QPLL_ENABLE {0}] [get_bd_cells axi_ad9371_tx_xcvr]
    delete_bd_objs [get_bd_intf_nets axi_ad9371_tx_xcvr_up_cm_0]
    endgroup
    startgroup
    set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] [get_bd_cells axi_ad9371_tx_xcvr]
    endgroup

    I've also modified the device tree as follows (update the sys-clk-select and use-cpll-enable parameters of the TX XCVR):

    diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts
    index 0b14689..7134fc6 100644
    --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts
    +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts
    @@ -247,8 +247,9 @@
                            #clock-cells = <1>;
                            clock-output-names = "tx_gt_clk", "tx_out_clk";
     
    -                       adi,sys-clk-select = <3>;
    +                       adi,sys-clk-select = <0>;
                            adi,out-clk-select = <3>;
    +                       adi,use-cpll-enable;
                    };
            };
     };

    After re-building and booting, I'm observing the following errors from the driver (I've pasted AD9371-specific lines):

    [    1.400633] ad9371 spi1.1: ad9371_probe : enter
    [    1.403177] ad9528 spi1.0: spi1.0 supply vcc not found, using dummy regulator
    [    1.430237] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.430260] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.430275] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.430290] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.430303] axi_adxcvr 84a60000.axi-adxcvr-rx: cpll: fb_div_N1=5
    [    1.430303] cpll: fb_div_N2=4
    [    1.430303] cpll: refclk_div=1
    [    1.430322] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 4915200 Hz Parent Rate 122880000 Hz
    [    1.430338] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.430352] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x28, val 0x28A
    [    1.430367] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.430381] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.430394] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x2A, val 0x8216
    [    1.430409] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.430424] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.430437] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x63, val 0x80C0
    [    1.430452] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.430467] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x6D val 0x3423
    [    1.430480] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x6D, val 0x3423
    [    1.430495] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x6D val 0x3423
    [    1.430509] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    1.430522] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x28, val 0x28A
    [    1.430537] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    1.430551] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    1.430564] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x2A, val 0x8216
    [    1.430579] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    1.430593] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x63 val 0x80C0
    [    1.430606] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x63, val 0x80C0
    [    1.430621] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x63 val 0x80C0
    [    1.430635] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x6D val 0x3423
    [    1.430648] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x6D, val 0x3423
    [    1.430663] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x6D val 0x3423
    [    1.430705] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.430719] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.430733] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.430747] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.430760] axi_adxcvr 84a60000.axi-adxcvr-rx: cpll: fb_div_N1=5
    [    1.430760] cpll: fb_div_N2=4
    [    1.430760] cpll: refclk_div=1
    [    1.431841] axi_adxcvr 84a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (16.01.a) using GTH4 at 0x84A60000 mapped to 0xffffff800931e000. Number of lanes: 2.
    [    1.431955] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_work_func: setting MMCM on RX rate 122880000
    [    1.431989] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.432004] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.432019] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.432033] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.432046] axi_adxcvr 84a60000.axi-adxcvr-rx: cpll: fb_div_N1=5
    [    1.432046] cpll: fb_div_N2=4
    [    1.432046] cpll: refclk_div=1
    [    1.432081] axi_adxcvr 84a50000.axi-adxcvr-rx-os: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.432095] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.432110] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.432124] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.432165] axi_adxcvr 84a50000.axi-adxcvr-rx-os: cpll: fb_div_N1=5
    [    1.432165] cpll: fb_div_N2=4
    [    1.432165] cpll: refclk_div=1
    [    1.432185] axi_adxcvr 84a50000.axi-adxcvr-rx-os: adxcvr_clk_set_rate: Rate 4915200 Hz Parent Rate 122880000 Hz
    [    1.432200] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.432213] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 256, reg 0x28, val 0x28A
    [    1.432229] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.432243] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.432256] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 256, reg 0x2A, val 0x8216
    [    1.432272] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.432286] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.432299] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 256, reg 0x63, val 0x80C0
    [    1.432314] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.432329] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x6D val 0x3423
    [    1.432342] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 256, reg 0x6D, val 0x3423
    [    1.432357] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x6D val 0x3423
    [    1.432372] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    1.432385] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 257, reg 0x28, val 0x28A
    [    1.432400] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    1.432414] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    1.432427] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 257, reg 0x2A, val 0x8216
    [    1.432442] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    1.432457] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x63 val 0x80C0
    [    1.432470] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 257, reg 0x63, val 0x80C0
    [    1.432485] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x63 val 0x80C0
    [    1.432499] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x6D val 0x3423
    [    1.432512] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_write: drp_port: 257, reg 0x6D, val 0x3423
    [    1.432528] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 257, reg 0x6D val 0x3423
    [    1.432564] axi_adxcvr 84a50000.axi-adxcvr-rx-os: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.432579] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.432593] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.432608] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.432621] axi_adxcvr 84a50000.axi-adxcvr-rx-os: cpll: fb_div_N1=5
    [    1.432621] cpll: fb_div_N2=4
    [    1.432621] cpll: refclk_div=1
    [    1.433842] axi_adxcvr 84a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (16.01.a) using GTH4 at 0x84A50000 mapped to 0xffffff8009325000. Number of lanes: 2.
    [    1.433988] axi_adxcvr 84a50000.axi-adxcvr-rx-os: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.434004] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.434019] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.434033] axi_adxcvr 84a50000.axi-adxcvr-rx-os: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.434047] axi_adxcvr 84a50000.axi-adxcvr-rx-os: cpll: fb_div_N1=5
    [    1.434047] cpll: fb_div_N2=4
    [    1.434047] cpll: refclk_div=1
    [    1.434064] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.434078] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
    [    1.434093] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.434107] axi_adxcvr 84a60000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.434120] axi_adxcvr 84a60000.axi-adxcvr-rx: cpll: fb_div_N1=5
    [    1.434120] cpll: fb_div_N2=4
    [    1.434120] cpll: refclk_div=1
    [    1.434154] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.434168] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0x1E0
    [    1.434182] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.434196] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.434209] axi_adxcvr 84a80000.axi-adxcvr-tx: cpll: fb_div_N1=5
    [    1.434209] cpll: fb_div_N2=4
    [    1.434209] cpll: refclk_div=1
    [    1.434227] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_set_rate: Rate 2457600 Hz Parent Rate 122880000 Hz
    [    1.434242] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.434255] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x28, val 0x28A
    [    1.434270] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.434284] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.434297] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x2A, val 0x8216
    [    1.434313] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.434327] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0x1E0
    [    1.434340] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x7C, val 0x1E0
    [    1.434355] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0x1E0
    [    1.434369] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7A val 0x2005
    [    1.434382] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x7A, val 0x2005
    [    1.434397] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7A val 0x2005
    [    1.434411] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    1.434424] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x28, val 0x28A
    [    1.434439] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    1.434453] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    1.434466] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x2A, val 0x8216
    [    1.434481] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    1.434495] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7C val 0x1E0
    [    1.434508] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x7C, val 0x1E0
    [    1.434523] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7C val 0x1E0
    [    1.434537] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7A val 0x2005
    [    1.434550] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x7A, val 0x2005
    [    1.434566] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7A val 0x2005
    [    1.434580] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x28 val 0x28A
    [    1.434593] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x28, val 0x28A
    [    1.434608] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x28 val 0x28A
    [    1.434622] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x2A val 0x8216
    [    1.434635] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x2A, val 0x8216
    [    1.434650] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x2A val 0x8216
    [    1.434664] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7C val 0x1E0
    [    1.434677] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x7C, val 0x1E0
    [    1.434692] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7C val 0x1E0
    [    1.434706] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7A val 0x2005
    [    1.434719] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x7A, val 0x2005
    [    1.434734] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7A val 0x2005
    [    1.434748] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x28 val 0x28A
    [    1.434761] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x28, val 0x28A
    [    1.434776] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x28 val 0x28A
    [    1.434790] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x2A val 0x8216
    [    1.434803] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x2A, val 0x8216
    [    1.434818] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x2A val 0x8216
    [    1.434832] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7C val 0x1E0
    [    1.434845] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x7C, val 0x1E0
    [    1.434860] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7C val 0x1E0
    [    1.434874] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7A val 0x2005
    [    1.434887] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x7A, val 0x2005
    [    1.434902] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7A val 0x2005
    [    1.434938] axi_adxcvr 84a50000.axi-adxcvr-rx-os: adxcvr_work_func: setting MMCM on RX rate 122880000
    [    1.434953] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_work_func: setting MMCM on TX rate 61440000
    [    1.435020] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    1.435035] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0x1E0
    [    1.435049] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    1.435063] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    1.435076] axi_adxcvr 84a80000.axi-adxcvr-tx: cpll: fb_div_N1=5
    [    1.435076] cpll: fb_div_N2=4
    [    1.435076] cpll: refclk_div=1
    [    1.435241] axi_adxcvr 84a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (16.01.a) using GTH4 at 0x84A80000 mapped to 0xffffff800932d000. Number of lanes: 4.
    ...
    [    6.566317] ad9371 spi1.1: ad9371_probe : enter
    [    6.571974] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_round_rate: Rate 4915200 Hz Parent Rate 122880000 Hz
    [    6.581905] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_set_rate: Rate 4915200 Hz Parent Rate 122880000 Hz
    [    6.591708] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    6.600993] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x28, val 0x28A
    [    6.610457] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    6.619744] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    6.629118] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x2A, val 0x8216
    [    6.638669] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    6.648047] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0x1E0
    [    6.657330] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x7C, val 0xE0
    [    6.666711] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0xE0
    [    6.675909] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7A val 0x2005
    [    6.685282] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x7A, val 0x2005
    [    6.694833] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7A val 0x2005
    [    6.704208] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    6.713495] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x28, val 0x28A
    [    6.722959] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x28A
    [    6.732247] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    6.741621] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x2A, val 0x8216
    [    6.751172] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
    [    6.760546] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7C val 0x1E0
    [    6.769834] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x7C, val 0xE0
    [    6.779211] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7C val 0xE0
    [    6.788415] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7A val 0x2005
    [    6.797786] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x7A, val 0x2005
    [    6.807338] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7A val 0x2005
    [    6.816715] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x28 val 0x28A
    [    6.825999] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x28, val 0x28A
    [    6.835463] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x28 val 0x28A
    [    6.844751] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x2A val 0x8216
    [    6.854125] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x2A, val 0x8216
    [    6.863676] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x2A val 0x8216
    [    6.873052] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7C val 0x1E0
    [    6.882339] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x7C, val 0xE0
    [    6.891715] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7C val 0xE0
    [    6.900916] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7A val 0x2005
    [    6.910290] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x7A, val 0x2005
    [    6.919841] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7A val 0x2005
    [    6.929216] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x28 val 0x28A
    [    6.938503] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x28, val 0x28A
    [    6.947967] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x28 val 0x28A
    [    6.957256] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x2A val 0x8216
    [    6.966629] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x2A, val 0x8216
    [    6.976180] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x2A val 0x8216
    [    6.985554] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7C val 0x1E0
    [    6.994842] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x7C, val 0xE0
    [    7.004219] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7C val 0xE0
    [    7.013420] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7A val 0x2005
    [    7.022794] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x7A, val 0x2005
    [    7.032345] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7A val 0x2005
    [    7.041719] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 122880000 Hz
    [    7.050401] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0xE0
    [    7.059603] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x28A
    [    7.068891] axi_adxcvr 84a80000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
    [    7.078268] axi_adxcvr 84a80000.axi-adxcvr-tx: cpll: fb_div_N1=5
    [    7.078268] cpll: fb_div_N2=4
    [    7.078268] cpll: refclk_div=1
    [    7.090248] ad9371 spi1.1: ad9371_update_sysref: setting SYSREF for LMFC rate 3840000 Hz
    [    7.098409] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_work_func: setting MMCM on TX rate 122880000
    ...
    [   12.427739] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_enable: TX
    [   12.635049] axi_adxcvr 84a80000.axi-adxcvr-tx: TX Error: 0
    [   12.640462] ad9371 spi1.1: jesd_tx_clk enable failed (-5)
    [   12.645841] ad9371 spi1.1: ad9371_update_sysref: setting SYSREF for LMFC rate 3840000 Hz
    [   17.969390] axi_adxcvr 84a80000.axi-adxcvr-tx: adxcvr_clk_enable: TX
    [   18.176697] axi_adxcvr 84a80000.axi-adxcvr-tx: TX Error: 0
    [   18.182109] ad9371 spi1.1: jesd_tx_clk enable failed (-5)
    [   18.187510] ad9371: probe of spi1.1 failed with error -5
    

    The probe is failing here:

    Relevant lines of code in the drivers include:

    Perhaps I missed something in the switch from QPLL to CPLL?

    Regards,

    -Jeff