I am working with the ADRV9371/ZCU102 reference design and am trying to program the ADRV9371 with a profile for 204.8 MSPS transmit. The AD9371 driver (and supporting drivers) appear to turn this into a request for JESD lane rate of 4.096 GHz. The default device tree and design appear to be set to use QPLL for the transmit lanes.
The requested lane rate of 4.096 GHz would require a QPLL VCO of 8.192 GHz (twice the lane rate). The Xilinx documentation UG576 lists two VCO bands for the QPLL, with the lower band supporting 8.192 GHz, but the software driver appears to be hardcoded to the upper band only (xilinx_transceiver.c).
Do the axi_adxcvr/util_adxcvr cores support both QPLL bands listed in UG576?