ADRV9009
Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com
AD9361
Recommended for New Designs
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and
4G base station applications....
Datasheet
AD9361 on Analog.com
AD9528
Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
Datasheet
AD9528 on Analog.com
I'm interested in designing an FMC card with 4 RX coherent channels for MIMO using two ADRV9009 chips. Are there are any design considerations for doing so? My team has done this with the AD9361 using the FMCOMMS5 as a basis. The axi_ad9361 core provided the l_clk output and clk input ports to control clocking between two chips and software handled the multichip synchronization procedure to phase lock the RX clocks. Is there an equivalent with the axi_adrv9009 core?
My current design approach is as follows:
Here's a rough block diagram:
My questions for my clarification: