Designing with multiple ADRV9009 chips

Question

I'm interested in designing an FMC card with 4 RX coherent channels for MIMO using two ADRV9009 chips. Are there are any design considerations for doing so? My team has done this with the AD9361 using the FMCOMMS5 as a basis. The axi_ad9361 core provided the l_clk output and clk input ports to control clocking between two chips and software handled the multichip synchronization procedure to phase lock the RX clocks. Is there an equivalent with the axi_adrv9009 core? My current design approach is as follows: 
 
 Keep util_adrv9009_xcvr to 4 RX channels (I'm not planning on using the RX_OS ports) 
 Drive axi_adrv9009_rx_clkgen with rx_out_clk_0 
 Drive adrv9009_core cores adc_clk with axi_adrv9009_rx_clkgen/clk_0 
 
 Here's a rough block diagram:

My questions for my clarification: 
 
 Can we rely JESD synchronization to get coherent RX data? Assuming an AD9528 drives both chips and proper synchronization procedures. 
 Should each ADRV9009 instead have its own instance of util_adxcvr and clocking?
 
 If so, how can the cores be internally synchronous in the FPGA

AdrianC · Accepted Answer

Hello, 
 We have under development a branch for a project that has two adrv9009's on the same board: https://github.com/analogdevicesinc/hdl/tree/prototype_som_2018_r2 .We are still working on software, testing and validation, but this is the architecture that we think will work with our JESD204B Interface framework. 
 Your approach seems fine. 
 For sample level deterministic latency, the device clock (driving what currently is driven by axi_adrv9009_rx_clkgen/clk_0) should be generated along with sysref by the AD9528, and not by clockgen. We are using it because we only have a reference clock and may configure RX/TX/OBS with different rates and we don't have additional clocks from the AD9528 to FPGA. Depending on the FPGA you are using and the sampling rates, the device clock can be the same with the transceiver reference clock or it can be a different clock all together, being fed to the FPGA through a clock capable pin. 
 Maybe somebody from the https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/ forum can give additional pointers regarding getting coherent RX data from the chip. 
 Regards, 
 Adrian)

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Designing with multiple ADRV9009 chips